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AD568SQ Arkusz danych(PDF) 8 Page - Analog Devices |
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AD568SQ Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 14 page AD568 REV. A –8– The variations in settling times can be attributed to differences in the rise time and current driving capabilities of the various families. Differences in the glitch impulse are predominantly de- pendent upon the variation in data skew. Variations in these specs occur not only between logic families, but also between different gates and latches within the same family. When select- ing a gate to drive the AD568 logic input, pay particular atten- tion to the propagation delay time specs: tPLH and tPHL. Selecting the smallest delays possible will help to minimize the settling time, while selection of gates where tPLH and tPHL are closely matched to one another will minimize the glitch impulse resulting from data skew. Of the common latches, the 74374 oc- tal flip-flop provides the best performance in this area for many of the logic families mentioned above. *FAST is a registered trademark of Fairchild Camera and Instrumentation Corporation. 1A 1B 2A 2B 3A 3B 4A 4B VCC 1V 2V 3V 4V STROBE GND 1A 1B 2A 2B 3A 3B 4A 4B VCC 1V 2V 3V 4V STROBE GND 1A 1B 2A 2B 3A 3B 4A 4B VCC 1V 2V 3V 4V STROBE GND 1 2 3 4 5 6 7 8 9 10 11 12 VCC REFCOM ACOM THCON VEE IBPO IOUT RL RSPAN VTH LCOM RSPAN AD568 +15V –15V VOUT 1k +5V +5V CLOCK IN WORD A 12 12 WORD B SELECT 74158 SELECT 74158 SELECT 74158 Figure 13. Test Setup for Glitch Impulse and Settling Time Measurements Settling Time Considerations As can be seen from Table I and the specifications page, the set- tling time of the AD568 is application dependent. The fastest settling is achieved in the current-output mode, since the volt- age output mode requires the output capacitance to be charged to the appropriate voltage. The DAC’s relatively large output current helps to minimize this effect, but settling-time sensitive applications should avoid any unnecessary parasitic capacitance at the output node of voltage output configurations. Direct mea- surement of the fine scale DAC settling time, even in the voltage output mode, is extremely tricky: analog scope front ends are generally incapable of recovering from overdrive quickly enough to give an accurate settling representation. The plot shown in Figure 14 was obtained using Data Precision’s 640 16-bit sam- pling head, which features the quick overdrive recovery charac- teristic of sampling approaches combined with high accuracy and relatively small thermal tail. TIME – ns 0 120 20 40 60 80 100 1.026 1.024 1.022 Figure 14. Zero to Full-Scale Settling Glitch Considerations In many high-speed DAC applications, glitch performance is a critical specification. In a conventional DAC architecture such as the AD568 there are two basic glitch mechanisms: data skew and digital feedthrough. A thorough understanding of these sources can help the user to minimize glitch in any application. DIGITAL FEEDTHROUGH—As with any converter product, a high-speed digital-to-analog converter is forced to exist on the frontier between the noisy environment of high-speed digital logic and the sensitive analog domain. The problems of this in- terfacing are particularly acute when demands of high speed (greater than 10 MHz switching times) and high precision (12 bits or more) are combined. No amount of design effort can perfectly isolate the analog portions of a DAC from the spectral components of a digital input signal with a 2 ns risetime. Inevi- tably, once this digital signal is brought onto the chip, some of its higher frequency components will find their way to the sensi- tive analog nodes, producing a digital feedthrough glitch. To minimize the exposure to this effect, the AD568 has intention- ally omitted the on-board latches that have been included in many slower DACs. This not only reduces the overall level of digital activity on chip, it also avoids bringing a latch clock pulse on board, whose opposite edge inevitably produces a substantial glitch, even when the DAC is not supposed to be changing codes. Another path for digital noise to find its way onto a con- verter chip is through the reference input pin. The completely internal reference featured in the AD568 eliminates this noise input, providing a greater degree of signal integrity in the analog portions of the chip. DATA SKEW—The AD568, like many of its slower predeces- sors, essentially uses each digital input line to switch a separate, weighted current to either the output (IOUT) or some other node (ANALOG COM). If the input bits are not changed simulta- neously, or if the different DAC bits switch at different speeds, then the DAC output current will momentarily take on some in- correct value. This effect is particularly troublesome at the “carry points”, where the DAC output is to change by only one LSB, but several of the larger current sources must be switched to realize this change. Data skew can allow the DAC output to move a substantial amount towards full scale or zero (depending upon the direction of the skew) when only a small transition is desired. Great care was taken in the design and layout of the AD568 to ensure that switching times of the DAC switches are symmetrical and that the length of the input data lines are short |
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