Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 10 -

Confidential Information

Table 2. CC Control Register Contents

#

7

6

5

4

3

2

1

0

0

Autocalibrate

Backlight 1

Test Data Enable Calibrate Radio

Encryption Type

Encrypt Key Load

2

Tx Monitor

Enable

Tx Phase

Polarity

Rx Radio Control

Polarity

Tx Radio Control

Polarity

Tx PHASE

Enable

Monitor

Enable

Receive

Enable

Transmit

Enable

4

Base Station Identity Code

5

Training Sequence Code

6

TxPA

Polarity

INT COUNT[8]

OCE OVERRIDE

Interrupt Counter

Override

Autocalibration

Type

Traffic Frame

Enable

Decryption

Enable

Encryption

Enable

7

BAND ENABLE

NMI Select

GPO10 Data

GPO10 Select

Data Ser. Select

DAIRESET

8

EEPROM Data

Output Enable

EERPOM

Clock

EEPROM

Enable

EERPOM

Data

9

Keypad Column

10

Keypad Row

28

EVBC Serial Port ( 15 : 8 )

29

EVBC Serial Port ( 7 : 0 )

30

Tx Data Delay

EVBC Rx-Buff. full EVBC Tx-Buf.empty

35

EVBC Reset

DSP Reset

CC Reset

37

Isolate

Synthesizer

Config. Dynam.

Synthesizer

Synthesizer

Interface active

Synthesizer Bit Count

38

Synthesizer

Enable Polarity

Synthesizer

Enable Type

Synthesizer

Clock Polarity

Synthesizer

Load Dynamic 1

Synthesizer

Load Dynamic 2

Synthesizer

Clock

39

Error Count

40

Synthesizer (31: 24)

41

Synthesizer (23: 16)

42

Synthesizer (15: 8)

43

Synthesizer (7: 0)

44

Backlight Duty Cycle

Synth. Interface

Power Enable

DSP Interface

Power Enable

Encryption Power

Enable

45

Coprocessor

Power Control

Output Clock

Enable

GP Power

Control

DSP Power

Control

Radio Power

Control

46

Encryption

SW-Reset

EVBC Interface

SW-Reset

DSP Interface

SW-Reset

Synthes. Interface

SW-Reset

47

INT CNT RST

Decode

SW-Reset

Deinterleave

SW-Reset

interleave

SW-Reset

Encode

SW-Reset

48

Interrupt Counter

49

EVBC Read

EVBC Tx Address

50

Modulate 1

Backlight LED Control

51

Version

72

Disable Synth.1

Disable Synth. 0 Synt. Enable Sel.

Synt. Mode

Pin Mode

73

TD ( 9 : 8 )

74

TD ( 7 : 0 )

75

TW ( 9 : 8 )

76

TW ( 7 : 0 )

77

GPO11 Data

GPO11 Select

IRQ5 Enable

IRQ4 Enable

IRQ3 Enable

IRQ2 Enable

FLASHPWD dis.

NMI Edge Pol.

78

IRQ5 active

IRQ4 active

IRQ3 active

IRQ2 active

79

GPIO9 OP En

GPIO8 OP En

GPIO9 Data

GPIO8 Data

88

GPO19 Sel

GPO18 Sel

GPO17 Sel

GPO19

GPO18

GPO17