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AD73360L Arkusz danych(PDF) 4 Page - Analog Devices |
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AD73360L Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 32 page REV. 0 AD73360L –4– t3 t2 t1 Figure 1. MCLK Timing TO OUTPUT PIN 2.1V 100 A 100 A IOL IOH CL 15pF Figure 2. Load Circuit for Timing Specifications t3 t1 t2 t13 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). t4 t5 t6 MCLK SCLK* Figure 3. SCLK Timing t11 t7 t9 t10 t12 t7 t8 SE (I) SCLK (O) SDIFS (I) SDI (I) SDOFS (O) SDO (O) THREE- STATE THREE- STATE THREE- STATE D15 D2 D1 D0 D14 D15 D1 D14 D15 D15 t8 D0 Figure 4. Serial Port (SPORT) VIN – dBm0 –85 5 –75 –65 –55 –45 –35 –25 –15 –5 80 70 –10 30 20 10 0 50 40 60 3.17 Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz) |
Podobny numer części - AD73360L |
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Podobny opis - AD73360L |
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