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AD7390AN Arkusz danych(PDF) 9 Page - Analog Devices |
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AD7390AN Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 12 page AD7390/AD7391 REV. 0 –9– The AD7390 should be powered directly from the system power supply. This arrangement, shown in Figure 22, employs an LC filter and separate power and ground connections to isolate the analog section from the logic switching transients. 100µF ELECT. 10-22µF TANT. 0.1µF CER. TTL/CMOS LOGIC CIRCUITS +5V POWER SUPPLY +5V +5V RETURN FERRITE BEAD: 2 TURNS, FAIR-RITE #2677006301 Figure 22. Use Separate Traces to Reduce Power Supply Noise Whether or not a separate power supply trace is available, how- ever, generous supply bypassing will reduce supply-line induced errors. Local supply bypassing consisting of a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic capacitor is recom- mended in all applications (Figure 23). C +2.7V to +5.5V 0.1 µF VOUT CLR SDI CLK LD 1 2 3 4 GND REF VDD AD7390 or AD7391 * 8 7 6 5 10 µF * OPTIONAL EXTERNAL REFERENCE BYPASS Figure 23. Recommended Supply Bypassing for the AD7390/AD7391 INPUT LOGIC LEVELS All digital inputs are protected with a Zener-type ESD protec- tion structure (Figure 24) that allows logic input voltages to ex- ceed the VDD supply voltage. This feature can be useful if the user is driving one or more of the digital inputs with a 5 V CMOS logic input-voltage level while operating the AD7390/ AD7391 on a 3 V power supply. If this mode of interface is used, make sure that the VOL of the 5 V CMOS meets the VIL input requirement of the AD7390/AD7391 operating at 3 V. See Figure 10 for a graph for digital logic input threshold versus operating VDD supply voltage. VDD LOGIC IN GND Figure 24. Equivalent Digital Input ESD Protection In order to minimize power dissipation from input-logic levels that are near the VIH and VIL logic input voltage specifications, a Schmitt trigger design was used that minimizes the input-buffer current consumption compared to traditional CMOS input stages. Figure 9 shows a plot of incremental input voltage versus supply current showing that negligible current consumption takes place when logic levels are in their quiescent state. The normal crossover current still occurs during logic transitions. A secondary advantage of this Schmitt trigger, is the prevention of false triggers that would occur with slow moving logic transi- tions when a standard CMOS logic interface or opto isolators are used. The logic inputs SDI, CLK, LD, CLR all contain the Schmitt trigger circuits. DIGITAL INTERFACE The AD7390/AD7391 have a double-buffered serial data input. The serial-input register is separate from the DAC register, which allows preloading of a new data value into the serial regis- ter without disturbing the present DAC values. A functional block diagram of the digital section is shown in Figure 4, while Table I contains the truth table for the control logic inputs. Three pins control the serial data input. Data at the Serial Data Input (SDI) is clocked into the shift register on the rising edge of CLK. Data is entered in MSB-first format. Twelve clock pulses are required to load the 12-bit AD7390 DAC value. If additional bits are clocked into the shift register, for example when a microcontroller sends two 8-bit bytes, the MSBs are ig- nored (Figure 25). The CLK pin is only enabled when Load (LD) is high. The lower resolution 10-bit AD7391 contains a 10-bit shift register. The AD7391 is also loaded MSB first with 10 bits of data. Again if additional bits are clocked into the shift register, only the last 10 bits clocked in are used. The Load pin (LD) controls the flow of data from the shift reg- ister to the DAC register. After a new value is clocked into the serial-input register, it will be transferred to the DAC register by the negative transition of the Load pin (LD). B15 X X B14 X X B13 X X B12 X X B11 D11 X B10 D!0 X B9 D9 D9 B8 D8 D8 B7 D7 D7 B6 D6 D6 B5 D5 D5 B4 D4 D4 B3 D3 D3 B2 D2 D2 B1 D1 D1 B0 D0 D0 MSB LSB LSB BYTE 0 BYTE 1 MSB D11_D0: 12-BIT AD7390 DAC VALUE; D9_D0 10-BIT AD7391 DAC VALUE X = DON’T CARE THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC Figure 25. Typical AD7390-Microprocessor Serial Data Input Forms |
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