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AD7568BP Arkusz danych(PDF) 4 Page - Analog Devices

Numer części AD7568BP
Szczegółowy opis  LC2MOS Octal 12-Bit DAC
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AD7568BP Arkusz danych(HTML) 4 Page - Analog Devices

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AD7568
REV. B
–4–
ABSOLUTE MAXIMUM RATINGS
1
(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
IOUT1 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
IOUT2 to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to VDD +0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .
±15 V
Input Current to Any Pin Except Supplies
2 . . . . . . . .
±10 mA
Operating Temperature Range
Commercial Plastic (B Versions) . . . . . . . . –40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300
°C
Power Dissipation (Any Package) to +75
°C . . . . . . . . 250 mW
Derates above +75
°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7568 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN DESCRIPTION
Pin
Description
VDD
Positive power supply. This is +5 V
± 5%.
DGND
Digital Ground.
AGND
Analog Ground.
VREFA – VREFH
DAC reference inputs.
RFBA – RFBH
DAC feedback resistor pins.
IOUTA – IOUTH
DAC current output terminals.
AGND
This pin connects to the back gates of the current steering switches. It should be connected to the signal ground
of the system.
CLKIN
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.
FSIN
Level-triggered control input (active low). This is the frame synchronization signal for the input data. When
FSIN
goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the
address bit is valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling
edge after FSIN goes low.
SDIN
Serial data input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining
bits following. Next comes the device address bit, A0. If this does not correspond to the logic level on pin A0,
the data is ignored. Finally come the three DAC select bits. These determine which DAC in the device is se-
lected for loading.
SDOUT
This shift register output allows multiple devices to be connected in a daisy chain configuration.
A0
Device address pin. This input gives the device an address. If DB3 of the serial input stream does not corre-
spond to this, the data which follows is ignored and not loaded to any input latch. However it will appear at
SDOUT irrespective of this.
LDAC
Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously updated with the
contents of the input latches.
CLR
Asynchronous CLR input. When this input is taken low, all DAC latch outputs go to zero.


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