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AD7709BRU Arkusz danych(PDF) 6 Page - Analog Devices |
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AD7709BRU Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 17 page AD7709 –6– REV. PrA January 2001 PRELIMINARY TECHNICAL DATA TIMINGCHARACTERISTICS1,2 (V DD = +3V ±10% or VDD = +5V ±10%;GND = 0 V:XTAL = 32.768kHz; Input Logic 0 = 0 V, Logic 1 = VDD unlessotherwisenoted) Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments t1 32.768 kHz typ Crystal Oscillator Frequency. t2 50 ns min RESET Pulse Width Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 3 t5 4 0 ns min SCLK Active Edge to Data Valid Delay 3 60 ns max VDD = +4.5 V to +5.5 V 80 ns max VDD = +2.7 V to +3.6 V t5A 4,5 0 ns min CS Falling Edge to Data Valid Delay3 60 ns max VDD = +4.5 V to +5.5 V 80 ns max VDD = +2.7 V to +3.6 V t6 100 ns min SCLK High Pulse Width t7 100 ns min SCLK Low Pulse Width t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 3 t9 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge 3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulse Width t15 100 ns min SCLK Low Pulse Width t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1 Sampletestedduringinitialreleasetoensurecompliance.Allinputsignalsarespecifiedwithtr=tf=5ns(10%to90%ofV DD)andtimedfromavoltagelevelof1.6V. 2 SeeFigures1and2. 3 SCLKactiveedgeisfallingedgeofSCLK. 4 ThesenumbersaremeasuredwiththeloadcircuitofFigure3anddefinedasthetimerequiredfortheoutputtocrosstheV OL orVOHlimits. 5 Thisspecificationonlycomesintoplayif CSgoeslowwhileSCLKislow.ItisrequiredprimarilyforinterfacingtoDSPmachines. 6 Thesenumbersarederivedfromthemeasuredtimetakenbythedataoutputtochange0.5 VwhenloadedwiththecircuitofFigure3.Themeasurednumberisthenextrapolatedbacktoremoveeffectsofchargingor dischargingthe50pFcapacitor.Thismeansthatthetimesquotedinthetimingcharacteristicsarethetruebusrelinquishtimesofthepartandassuchareindependentofexternalbusloadingcapacitances. 7 RDYreturnshighafterthefirstreadfromthedeviceafteranoutputupdate.Thesamedatacanbereadagain,ifrequired,whileRDYishigh,althoughcareshouldbetakenthatsubsequentreadsdonotoccurcloseto thenextoutputupdate. |
Podobny numer części - AD7709BRU |
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Podobny opis - AD7709BRU |
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