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AD7709BRU Arkusz danych(PDF) 9 Page - Analog Devices

Numer części AD7709BRU
Szczegółowy opis  16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port
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Strona internetowa  http://www.analog.com
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AD7709
–9–
REV. PrA
January 2001
PRELIMINARY TECHNICAL DATA
11
REFIN2(-)
Negative reference input. This reference input can lie anywhere between GND
and VDD-1V.
12
P2/SW2
P2 can act as a general purpose Input/Output bit referenced between VDD and
GND or as a low-side power switch to PWRGND..
13
PWRGND
Ground point for the low-side power switches SW2 and SW1. PWRGND
must be tied to GND.
14
P1/SW1
P1 can act as a general purpose Output bit referenced between VDD and GND
or as a low-side power switch to PWRGND.
15
RESET
Digital input used to reset the ADC to its power-on-reset status. This pin has
a weak pull-up internally to DVDD.
16
SCLK
Serial clock input for data transfers to and from the ADC. The SCLK has a
schmitt triggered input making the interface suitable for opto-isolated applica-
tions. The serial clock can be continuous with all data transmitted in a con-
tinuous train of pulses. Alternatively, it can be noncontinuous clock with the
information being transmitted to or from the AD7709 in smaller batches of
data.
17
CS
Chip Select Input. This is an active low logic input used to select the
AD7709.
CS can be used to select the AD7709 in systems with more than one
device on the serial bus or as a frame synchronisation signal in communicating
with the device.
CS can be hardwired low allowing the AD7709 to be operated
in three-wire mode with SCLK, DIN and DOUT used to interface with the
device.
18
RDY
RDY is a logic low status output from the AD7709. RDY is low if the ADC
has valid data in its data register. This output returns high on completion of a
read operation from the data register. If data is not read,
RDY will return high
prior to the next update indicating to the user that a read operation should not
be initiated.
19
D O U T
Serial data output with serial data being read from the output shift register of
the ADC. The output shift register can contain data from any of the on-chip
data, calibration or control registers.
20
D I N
Serial Data Input with serial data being written to the input shift register on
the AD7709. Data in this shift register is transferred to the control registers
within the ADC depending on the selection bits of the Communications regis-
ter.
21
G N D
Ground Reference point for the AD7709.
22
VDD
Supply voltage, 3V or 5V nominal.
23
XTAL2
Output from the 32kHz crystal oscillator inverter.
24
XTAL1
Input to the 32kHz crystal oscillator inverter.


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