AD7712 datasheet(5/28 Pages) AD

Numer części	AD7712

Szczegółowy opis	LC2MOS Signal Conditioning ADC

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Producent	AD [Analog Devices]

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2

–5–

REV. E

AD7712

TIMING CHARACTERISTICS1, 2

Limit at TMIN, TMAX

Parameter

(A, S Versions)

Units

Conditions/Comments

fCLK IN

4, 5

Master Clock Frequency: Crystal Oscillator or

Externally Supplied

400

kHz min

AVDD = +5 V

± 5%

10

MHz max

For Specified Performance

8

MHz

AVDD = +5.25 V to +10.5 V

tCLK IN LO

0.4

× t

CLK IN

ns min

Master Clock Input Low Time; tCLK IN = 1/fCLK IN

tCLK IN HI

0.4

× t

CLK IN

ns min

Master Clock Input High Time

tr

6

50

ns max

Digital Output Rise Time; Typically 20 ns

tf

6

50

ns max

Digital Output Fall Time; Typically 20 ns

t1

1000

ns min

SYNC Pulsewidth

Self-Clocking Mode

t2

0

ns min

DRDY to RFS Setup Time; t

CLK IN = 1/fCLK IN

t3

0

ns min

DRDY to RFS Hold Time

t4

2

× t

CLK IN

ns min

A0 to

RFS Setup Time

t5

0

ns min

A0 to

RFS Hold Time

t6

4

× t

CLK IN + 20

ns max

RFS Low to SCLK Falling Edge

t7

7

4

× t

CLK IN + 20

ns max

Data Access Time (

RFS Low to Data Valid)

t8

7

tCLK IN/2

ns min

SCLK Falling Edge to Data Valid Delay

tCLK IN/2 + 30

ns max

t9

tCLK IN/2

ns nom

SCLK High Pulsewidth

t10

3

× t

CLK IN/2

ns nom

SCLK Low Pulsewidth

t14

50

ns min

A0 to

TFS Setup Time

t15

0

ns min

A0 to

TFS Hold Time

t16

4

× t

CLK IN + 20

ns max

TFS to SCLK Falling Edge Delay Time

t17

4

× t

CLK IN

ns min

TFS to SCLK Falling Edge Hold Time

t18

0

ns min

Data Valid to SCLK Setup Time

t19

10

ns min

Data Valid to SCLK Hold Time

(DVDD = +5 V

5%; AVDD = +5 V or +10 V

3

5%; VSS = 0 V or –5 V

5%; AGND = DGND =

0 V; fCLKIN =10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)

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