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AD7713 Arkusz danych(PDF) 4 Page - Analog Devices

Numer części AD7713
Szczegółowy opis  LC2MOS Loop-Powered Signal Conditioning ADC
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD7713 Arkusz danych(HTML) 4 Page - Analog Devices

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Parameter
A, S Versions1
Units
Conditions/Comments
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage
+5 to +10
V nom
±5% for Specified Performance
DVDD Voltage
16
+5
V nom
±5% for Specified Performance
Power Supply Currents
AVDD Current
0.6
mA max
AVDD = +5 V
0.7
mA max
AVDD = +10 V
DVDD Current
0.5
mA max
fCLK IN = 1 MHz. Digital Inputs 0 V to DVDD
1
mA max
fCLK IN = 2 MHz. Digital Inputs 0 V to DVDD
Power Supply Rejection
17
Rejection w.r.t. AGND
(AVDD and DVDD)
See Note 18
dB typ
Power Dissipation
Normal Mode
5.5
mW max
AVDD = DVDD = +5 V, fCLK IN = 1 MHz; Typically 3.5 mW
Standby (Power-Down) Mode
300
µW max
AVDD = DVDD = +5 V, Typically 150 µW
NOTES
16The
±5% tolerance on the DV
DD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.
17Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz or 60 Hz.
18PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
Specifications subject to change without notice.
AD7713–SPECIFICATIONS
REV. C
–4–
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(A, S Versions)
Units
Conditions/Comments
fCLK IN
3, 4
400
kHz min
Master Clock Frequency: Crystal Oscillator or
2
MHz max
Externally Supplied for Specified Performance
tCLK IN LO
0.4
× t
CLK IN
ns min
Master Clock Input Low Time; tCLK IN = 1/fCLK IN
tCLK IN HI
0.4
× t
CLK IN
ns min
Master Clock Input High Time
tr
5
50
ns max
Digital Output Rise Time; Typically 20 ns
tf
5
50
ns max
Digital Output Fall Time; Typically 20 ns
t1
1000
ns min
SYNC
Pulse Width
Self-Clocking Mode
t2
0
ns min
DRDY
to RFS Setup Time
t3
0
ns min
DRDY
to RFS Hold Time
t4
2
× t
CLK IN
ns min
A0 to RFS Setup Time
t5
0
ns min
A0 to RFS Hold Time
t6
4
× t
CLK IN + 20
ns max
RFS
Low to SCLK Falling Edge
t7
6
4
× t
CLK IN +20
ns max
Data Access Time (RFS Low to Data Valid)
t8
6
tCLK IN/2
ns min
SCLK Falling Edge to Data Valid Delay
tCLK IN/2 + 30
ns max
t9
tCLK IN/2
ns nom
SCLK High Pulse Width
t10
3
× t
CLK IN/2
ns nom
SCLK Low Pulse Width
t14
50
ns min
A0 to TFS Setup Time
t15
0
ns min
A0 to TFS Hold Time
t16
4
× t
CLK IN + 20
ns max
TFS
to SCLK Falling Edge Delay Time
t17
4
× t
CLK IN
ns min
TFS
to SCLK Falling Edge Hold Time
t18
0
ns min
Data Valid to SCLK Setup Time
t19
10
ns min
Data Valid to SCLK Hold Time
(DVDD = +5 V
± 5%; AV
DD = +5 V or +10 V
± 5%; AGND = DGND = 0 V; f
CLKIN =2 MHz;
Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)


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