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AD7866ARU Arkusz danych(PDF) 4 Page - Analog Devices |
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AD7866ARU Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 20 page REV. 0 AD7866 –4– 1.6V 200 AIOL 200 A IOH CL 50pF TO OUTPUT PIN Figure 1. Load Circuit for Digital Output Timing Specifications WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7866 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS 1 (TA = 25 oC unless otherwise noted) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDRIVE to DGND . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V VDRIVE to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND . . . . . . . . . . . –0.3 V to +7 V VREF to AGND . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Digital Output Voltage to DGND . . –0.3 V to VDRIVE + 0.3 V Input Current to Any Pin Except Supplies 2 . . . . . . . . ±10 mA Operating Temperature Range Commercial (A, B Versions) . . . . . . . . . . . . . –40 oC to +85oC Storage Temperature Range . . . . . . . . . . . . –65 oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 oC TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . 143 °C/W (TSSOP) JC Thermal Impedance . . . . . . . . . . . . . 45 °C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215 °C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220 °C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up. TIMING SPECIFICATIONS1 (V DD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.) Limit at Parameter TMIN, TMAX Unit Description fSCLK 2 10 kHz min 20 MHz max tCONVERT 16 × t SCLK ns max tSCLK = 1/fSCLK 800 ns max fSCLK = 20 MHz tQUIET 50 ns max Minimum Time Between End of Serial Read and Next Falling Edge of CS t2 10 ns min CS to SCLK Setup Time t3 3 25 ns max Delay from CS Until D OUTA and DOUTB Three-State Disabled t4 3 40 ns max Data Access Time After SCLK Falling Edge. VDRIVE 3 V, CL = 50 pF; VDRIVE < 3 V, CL = 25 pF t5 0.4 tSCLK ns min SCLK Low Pulsewidth t6 0.4 tSCLK ns min SCLK High Pulsewidth t7 10 ns min SCLK to Data Valid Hold Time t8 4 25 ns max CS Rising Edge to D OUTA, DOUTB, High Impedance t9 4 10 ns min SCLK Falling Edge to DOUTA, DOUTB, High Impedance 50 ns max SCLK Falling Edge to DOUTA, DOUTB, High Impedance NOTES 1Sample tested at 25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DRIVE) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the CLK input is 40/60 to 60/40. 3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4t 8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t 8 and t9 quoted in the timing characteristics are the true bus relinquish times of the part and are independent of the bus loading. Specifications subject to change without notice. |
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