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AD7886 Arkusz danych(PDF) 8 Page - Analog Devices |
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AD7886 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 16 page AD7886 –8– REV. B BIPOLAR OFFSET AND GAIN ADJUSTMENT In applications where absolute accuracy is important, offset and gain error can be adjusted to zero. Offset is adjusted by trim- ming the voltage at the VIN1 or VIN2 input when the analog in- put is at zero volts. This can be achieved by adjusting the offset of an external amplifier used to drive either of these inputs (see A1 in Figure 9). The trim procedure is as follows: Apply zero volts at AIN and adjust the offset of A1 until the ADC output code flickers between 0111 1111 1111 and 1000 0000 0000. Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC posi- tive full scale). Adjusting the reference, as in Figure 9, will trim the positive gain error only. The trim procedure is as follows: Apply a voltage of 4.99756 V, (FS/2–1 LSB) at AIN and adjust R3 until the output code flickers between 1111 1111 1110 and 1111 11111111. If the first code transition needs adjusting, a gain trim must be included in the analog signal path. The trim procedure will then consist of applying an analog signal of –4.99756 V (–FS/2+1 LSB) and adjusting the trim until the output code flickers between 0000 0000 0000 and 0000 0000 0001. AD7886* SUM + – AD586 VOUT +VIN GND +V C1 10 µF C2 0.1 µF AD707 VIN1 VIN2 AGND VSS VDD AIN R1 82k R2 56k R3 5k – + AD845 A1 5V + 5REF + 5V + 3.5V – VREF 5V – *ADDITIONAL PINS OMITTED FOR CLARITY 5V ± Figure 9. Bipolar Operation with Gain Error Adjust TIMING AND CONTROL Conversion start is controlled by the CONVST input (see Fig- ures 10 and 11). A high to low going edge on the CONVST in- put puts the track/hold amplifier into the hold mode. The ADC conversion procedure does not begin until a rising CONVST pulse edge occurs. The width of the CONVST pulse low time determines the track-to-hold settling time. The BUSY output, which indicates the status of the ADC, goes low while conver- sion is in progress. At the end of conversion BUSY returns high, indicating that new data is available on the AD7886’s output latches. The track/hold amplifier returns to the track mode at the end of conversion and remains there until the next CONVST pulse. Conversion starts must not be attempted while conversion is in progress as this will cause erroneous results. Data read operations are controlled by the CS and RD inputs. These digital inputs, when low, enable the AD7886’s three- state output latches. Note, these latches cannot be enabled dur- ing conversion. In applications where CS and RD are tied per- manently low, as in Figure 11, the data bus will go into the three-state condition at the start of conversion and return to its active state when conversion is complete. Tying CS and RD permanently low is useful when external latches are used to store the conversion results. The data bus becomes active before BUSY returns high at the end of conversion, so that BUSY can be used as a clocking signal for the external latches. A typical DSP application would have a timer connected to the CONVST input for precise sampling intervals. BUSY would be connected to the interrupt of a microprocessor that would be asserted at the end of every conversion. The microprocessor would then assert the CS and RD inputs and read the data from the ADC. For applications where both data reading and conver- sion control need to be managed by a microprocessor, a CONVST pulse can be decoded from the address bus. One decoding pos- sibility is that a write instruction to the ADC address starts a conversion, and a read instruction reads the conversion result. DATA VALID CONVST BUSY RD CS DATA HIGH IMPEDANCE t1 t 2 t 3 t CONV t 5 t 6 t 7 t 4 t10 t11 t12 t13 TRACK-TO-HOLD TRANSITION CONVERSION START HOLD TO TRACK TRANSITION Figure 10. Conversion Start and Data Read Timing Diagram DATA VALID CONVST BUSY DATA HIGH IMPEDANCE t1 t CONV t 8 t12 5 t 9 t t13 TRACK-TO-HOLD TRANSITION CONVERSION START HOLD TO TRACK TRANSITION Figure 11. Conversion Start and Data Read Timing Diagram, (CS = RD = 0 V) |
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