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AD7884AN Arkusz danych(PDF) 11 Page - Analog Devices |
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AD7884AN Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 16 page AD7884/AD7885 REV. C –11– If the noise in the converter is too high for an application, it can be reduced by oversampling and digital filtering. This involves sampling the input at higher than the required word rate and then averaging to arrive at the final result. The very fast conver- sion time of the AD7884/AD7885 makes it very suitable for oversampling. For example, if the required input bandwidth is 40 kHz, the AD7884/AD7885 could be oversampled by a factor of 2. This yields a 3 dB improvement in the effective SNR per- formance. The noise performance in the ±5 volt input range is now effectively 85 µV rms and the resultant spread of codes for 2500 conversions will be four. This is shown in Figure 15. 1500 0 1000 500 (X – 1) (X) (X + 1) (X + 2) CODE Figure 15. Histogram of 2500 Conversions of a DC Input Using a ×2 Oversampling Ratio Dynamic Performance With a combined conversion and acquisition time of 6 µs, the AD7884/AD7885 is ideal for wide bandwidth signal processing applications. Signal to (Noise + Distortion), Total Harmonic Distortion, Peak Harmonic or Spurious Noise and Intermodula- tion Distortion are all specified. Figure 16 shows a typical FFT plot of a 1.8 kHz, ± 5 V input after being digitized by the AD7884/AD7885. 0 –150 –60 –120 –90 –30 2048 POINT FFT f = 1.8kHz, ± 5V SINE WAVE f = 163kHz SNR = 87dB THD = –95dB IN SAMPLE Figure 16. AD7884/AD7885 FFT Plot Effective Number of Bits The formula for SNR (see Terminology section) is related to the resolution or number of bits in the converter. Rewriting the formula, below, gives a measure of performance expressed in effective number of bits (N). N = (SNR – 1.76)/6.02 16 10 80 13 11 20 12 0 15 14 60 40 FREQUENCY – kHz Figure 17. Effective Number of Bits vs. Frequency The effective number of bits for a device can be calculated from its measured SNR. Figure 17 shows a typical plot of effective number of bits versus frequency for the AD7884. The sampling frequency is 166 kHz. MICROPROCESSOR INTERFACING The AD7884/AD7885 is designed on a high speed process which results in very fast interfacing timing (Data Access Time of 57 ns max). The AD7884 has a full 16-bit parallel bus, and the AD7885 has an 8-bit wide bus. The AD7884, with its paral- lel interface, is suited to 16-bit parallel machines whereas the AD7885, with its byte interface, is suited to 8-bit machines. Some examples of typical interface configurations follow. AD7884 to MC68000 Interface Figure 18 shows a general interface diagram for the MC68000, 16-bit microprocessor to the AD7884. In Figure 18, conversion is initiated by bringing CSA low (i.e., writing to the appropriate address). This allows the processor to maintain control over the complete conversion process. In some cases it may be more desirable to control conversion independent from the processor. This can be done by using an external sampling timer. MC68000 AD7884 ADDRESS DECODE LOGIC CONVST CS RD DB15 – DB0 R/W DATA BUS ADDRESS BUS A23 – A1 D15 – D0 DTACK AS CSA CSB Figure 18. AD7884 to MC68000 Interface Once conversion has been started, the processor must wait until it is completed before reading the result. There are two ways of ensuring this. The first way is to simply use a software delay to wait for 6.5 µs before bringing CS and RD low to read the data. |
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