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AD7895AN-3 Arkusz danych(PDF) 9 Page - Analog Devices |
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AD7895AN-3 Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 12 page AD7895 –9– REV. 0 MICROPROCESSOR/MICROCONTROLLER INTERFACE The AD7895 provides a three-wire serial interface that can be used for connection to the serial ports of DSP processors and microcontrollers. Figures 6 through 9 show the AD7895 interfaced to a number of different microcontrollers and DSP processors. The AD7895 accepts an external serial clock, and as a result, in all interfaces shown here, the processor/controller is configured as the master, providing the serial clock with the AD7895 configured as the slave in the system. AD7895–8051 Interface Figure 6 shows an interface between the AD7895 and the 8XL51 microcontroller. The 8XL51 is configured for its Mode 0 serial interface mode. The diagram shows the simplest form of the interface where the AD7895 is the only part connected to the serial port of the 8XL51 and, therefore, no decoding of the serial read operations is required. AD7895 SDATA SCLK BUSY P3.0 P3.1 8X51/L51 P1.2 OR INT1 Figure 6. AD7895 to 8X51/L51 Interface To chip select the AD7895 in systems where more than one device is connected to the 8XL51’s serial port, a port bit configured as an output, from one of the 8XL51’s parallel ports can be used to gate on or off the serial clock to the AD7895. A simple AND function on this port bit and the serial clock from the 8XL51 will provide this function. The port bit should be high to select the AD7895 and low when it is not selected. The end of conversion is monitored by using the BUSY signal that is shown in the interface diagram of Figure 6. The BUSY line from the AD7895 is connected to the Port P1.2 of the 8XL51 so the BUSY line can be polled by the 8XL51. The BUSY line can be connected to the INT1 line of the 8XL51 if an interrupt driven system is preferred. These two options are shown in the diagram. Note also that the AD7895 outputs the MSB first during a read operation, while the 8XL51 expects the LSB first. Therefore, the data which is read into the serial buffer needs to be rear- ranged before the correct data format from the AD7895 appears in the accumulator. The serial clock rate from the 8XL51 is limited to significantly less than the allowable input serial clock frequency with which the AD7895 can operate. As a result, the time to read data from the part will actually be longer than the conversion time of the part. This means that the AD7895 cannot run at its maximum throughput rate when used with the 8XL51. AD7895–68HC11/L11 Interface An interface circuit between the AD7895 and the 68HC11/L11 microcontroller is shown in Figure 7. For the interface shown, the 68L11 SPI port is used, and the 68L11 is configured in its single-chip mode. The 68L11 is configured in the master mode with its CPOL bit set to a logic zero and its CPHA bit set to a logic one. As with the previous interface, the diagram shows the simplest form of the interface where the AD7895 is the only part connected to the serial port of the 68L11 and, therefore, no decoding of the serial read operations is required. AD7895 SDATA SCLK BUSY SCK MISO 68HC11/L11 PC2 OR IRQ Figure 7. AD7895 to 68HC11/L11 Interface Once again, to chip select the AD7895 in systems where more than one device is connected to the 68HC11’s serial port, a port bit configured as an output from one of the 68HC11’s parallel ports can be used to gate on or off the serial clock to the AD7895. A simple AND function on this port bit and the serial clock from the 68L11 will provide this function. The port bit should be high to select the AD7895 and low when it is not selected. The end of conversion is monitored by using the BUSY signal that is shown in the interface diagram of Figure 7. With the BUSY line from the AD7895 connected to the Port PC0 of the 68HC11/L11, the BUSY line can be polled by the 68HC11/L11. The BUSY line can be connected to the IRQ line of the 68HC11/L11 if an interrupt driven system is preferred. These two options are shown in the diagram. The serial clock rate from the 68HC11/L11 is limited to significantly less than the allowable input serial clock frequency with which the AD7895 can operate. As a result, the time to read data from the part will actually be longer than the conver- sion time of the part. This means that the AD7895 cannot run at its maximum throughput rate when used with the 68HC11/L11. AD7895–ADSP-2103/5 Interface An interface circuit between the AD7895 and the ADSP-2103/5 DSP processor is shown in Figure 8. In the interface shown, the RFS1 output from the ADSP-2103/5s SPORT1 serial port is used to gate the serial clock (SCLK1) of the ADSP-2103/5 before it is applied to the SCLK input of the AD7895. The RFS1 output is configured for active high operation. The BUSY line from the AD7895 is connected to the IRQ2 line of the ADSP-2103/5 so that at the end of conversion an interrupt is generated telling the ADSP-2103/5 to initiate a read operation. The interface ensures a noncontinuous clock for the AD7895’s serial clock input with only sixteen serial clock pulses provided and the serial clock line of the AD7895 remaining low between data transfers. The SDATA line from the AD7895 is connected to the DR1 line of the ADSP-2103/5’s serial port. |
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