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AD795JR Arkusz danych(PDF) 10 Page - Analog Devices |
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AD795JR Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 16 page AD795 REV. A –10– Leakage through the bulk of the circuit board will still occur with the guarding schemes shown in Figures 31 and 32. Stan- dard “G10” type printed circuit board material may not have high enough volume resistivity to hold leakages at the sub- picoampere level particularly under high humidity conditions. One option that eliminates all effects of board resistance is shown in Figure 33. The AD795’s sensitive input pin (either Pin 2 when connected as an inverter, or Pin 3 when connected as a follower) is bent up and soldered directly to a Teflon* insulated standoff. Both the signal input and feedback compo- nent leads must also be insulated from the circuit board by Teflon standoffs or low-leakage shielded cable. 1 2 3 4 8 7 6 5 AD795 AD795 TEFLON INSULATED STANDOFF INPUT SIGNAL LEAD INPUT PIN: PIN 2 FOR INVERTER OR PIN 3 FOR FOLLOWER PC BOARD Figure 33. Input Pin to Insulating Standoff Contaminants such as solder flux on the board’s surface and on the amplifier’s package can greatly reduce the insulation resis- tance between the input pin and those traces with supply or signal voltages. Both the package and the board must be kept clean and dry. An effective cleaning procedure is to first swab the surface with high grade isopropyl alcohol, then rinse it with deionized water and, finally, bake it at 100 °C for 1 hour. Poly- propylene and polystyrene capacitors should not be subjected to the 100 °C bake as they will be damaged at temperatures greater than 80 °C. Other guidelines include making the circuit layout as compact as possible and reducing the length of input lines. Keeping circuit board components rigid and minimizing vibration will reduce triboelectric and piezoelectric effects. All precision high impedance circuitry requires shielding from electrical noise and interference. For example, a ground plane should be used under all high value (i.e., greater than 1 M Ω) feedback resistors. In some cases, a shield placed over the resistors, or even the entire amplifier, may be needed to minimize electrical interference originating from other circuits. Referring to the equation in Figure 30, this coupling can take place in either, or both, of two different forms—coupling via time varying fields: dV dT CP or by injection of parasitic currents by changes in capacitance due to mechanical vibration: dCp dT V *Teflon is a registered trademark of E.I. du Pont Co. Both proper shielding and rigid mechanical mounting of components help minimize error currents from both of these sources. OFFSET NULLING The AD795’s input offset voltage can be nulled (mini-DIP package only) by using balance Pins 1 and 5, as shown in Figure 34. Nulling the input offset voltage in this fashion will introduce an added input offset voltage drift component of 2.4 µV/°C per millivolt of nulled offset. 1 6 5 4 3 2 AD795 7 +VS VOUT 100k Ω –VS + – Figure 34. Standard Offset Null Circuit The circuit in Figure 35 can be used when the amplifier is used as an inverter. This method introduces a small voltage in series with the amplifier’s positive input terminal. The amplifier’s input offset voltage drift with temperature is not affected. However, variation of the power supply voltages will cause offset shifts. 6 3 2 AD795 RI VOUT RF VI + – 499k Ω 499k Ω 200 Ω 0.1 µF 100k Ω +VS –VS + – Figure 35. Alternate Offset Null Circuit for Inverter |
Podobny numer części - AD795JR |
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Podobny opis - AD795JR |
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