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AD8016ARE Arkusz danych(PDF) 11 Page - Analog Devices |
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AD8016ARE Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 20 page REV. A AD8016 –11– FEEDBACK RESISTOR SELECTION In current feedback amplifiers, selection of feedback and gain resistors will have an impact on the MTPR performance, band- width and gain flatness. Care should be exercised in the selec- tion of these resistors so that optimum performance is achieved. The table below shows the recommended resistor values for use in a variety of gain settings. These values are suggested as a good starting point when designing for any application. Table I. Resistor Selection Guide Gain RF ( )RG ( ) +1 1 k ∞ –1 500 500 +2 650 650 +5 750 187 +10 1 k 111 BIAS PIN AND PWDN FEATURES The AD8016 is designed to cover both CO (Central Office) and CPE (Customer Premise Equipment) ends of an xDSL applica- tion. It offers full versatility in setting quiescent bias levels for the particular application from full ON to reduced bias (in three steps) to full OFF (via BIAS pin). This versatility gives the modem designer the flexibility to maximize efficiency while maintaining reasonable levels of Multitone Power Ratio (MTPR) performance. Optimizing driver efficiency while delivering the required DMT power is accomplished with the AD8016 through the use of on-chip power management features. Two digitally programmable logic pins, PWDN1 and PWDN0, may be used to select four different bias levels; 100%, 60%, 40%, and 25% of full quiescent power (see Table II). Table II. PWDN Code Selection Guide PWDN1 PWDN0 Code Code Quiescent Bias Level 1 1 100% (Full ON) 1 0 60% 0 1 40% 0 0 25% (Low ZOUT but Not OFF) X X Full OFF (High ZOUT via 250 µA Pulled Out of BIAS Pin) The bias level can be controlled with TTL logic levels (HI = 1) applied to PWDN1 and PWDN0 pins alone or in combination with BIAS control pin. The DGND or digital ground pin is the logic ground reference for PWDN1 and PWDN0 pins. In typical ADSL applications where ± 12 V or ± 6 V supplies (also single supplies) are used, the DGND pin is connected to analog ground. The BIAS control pin by itself is a means to continuously adjust the AD8016 internal biasing and thus quiescent current IQ. By pulling out a current of 0 µA (or open) to approximately 200 µA, the quiescent current can be adjusted from 100% (full ON) to a full OFF condition. The full OFF condition yields a high output impedance. Because of on-chip resistor variation of up to ±20% the actual amount of current required to fully shut down the AD8016 can vary. To institute a full chip shutdown, a pull- down current of 250 µA is recommended. See Figure 38 for logic drive circuit for complete amplifier shutdown. Figures 34 and 35 show the relationship between current pulled out of THEORY OF OPERATION The AD8016 is a current feedback amplifier with high (500 mA) output current capability. With a current feedback amplifier the current into the inverting input is the feedback signal and the open-loop behavior is that of a transimpedance, dVo/dIin or TZ. The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 37 shows a simplified model of a current feedback amplifier. Since RIN is proportional to 1/gm, the equivalent voltage gain is just TZ × gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields: V V G TS TS G R R O IN Z ZIN F =× +× + () () where: G R R R g F G IN m =+ =≈ 1 1 25 Ω Recognizing that G × RIN << RF for low gains, the familiar result of constant bandwidth with gain for current feedback amplifiers is evident, the 3 dB point being set when |TZ| = RF. Of course, for a real amplifier there are additional poles that contribute excess phase and there will be a value for RF below which the amplifier is unstable. Tolerance for peaking and desired flatness will determine the optimum RF in each application. TZ RIN IIN + + – RF VOUT RN RG VIN Figure 37. Simplified Block Diagram The AD8016 is the first current feedback amplifier capable of delivering 400 mA of output current while swinging to within 2 V of either power supply rail. This enables full CO ADSL performance on only 12 V rails, an immediate 20% power saving. The AD8016 is also unique in that it has a power management system included on-chip. It features four user programmable power levels (all of which provide a low output impedance of the driver), as well as the provision for complete shutdown (high impedance state). Also featured is a thermal shutdown with alarm signal. POWER SUPPLY AND DECOUPLING The AD8016 should be powered with a good quality (i.e., low noise) dual supply of ±12 V for the best distortion and Multi- tone Power Ratio (MTPR) performance. Careful attention must be paid to decoupling the power supply pins. A 10 µF capacitor located in near proximity to the AD8016 is required to provide good decoupling for lower frequency signals. In addition, 0.1 µF decoupling capacitors should be located as close to each of the four power supply pins as is physically possible. All ground pins should be connected to a common low impedance ground plane. |
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