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AD8200 Arkusz danych(PDF) 8 Page - Analog Devices |
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AD8200 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 8 page REV. 0 AD8200 –8– HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT Figure 11 is another refinement of Figure 1, including gain adjustment and low-pass filtering. –IN GND A1 A2 +IN NC +VS OUT AD8200 5V OUTPUT 4V/AMP INDUCTIVE LOAD POWER DEVICE 4 TERM SHUNT CLAMP DIODE BATTERY 14V COMMON C VOS/IB NULL 191k 20k 5% CALIBRATION RANGE FC = 0.796Hz – F (0.22 F FOR f = 3.6 Hz) NC = NO CONNECT Figure 11. High-Line Current Sensor Interface. Gain = ×40, Single-Pole, Low-Pass Filter A power device that is either ‘ON’ or ‘OFF’ controls the current in the load. The average current is proportional to the duty cycle of the input pulse, and is sensed by a small value resistor. The average differential voltage across the shunt is typically 100 mV, although its peak value will be higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, on the other hand, extends from roughly 1 V above ground, when the switch is ‘ON,’ to about 1.5 V above the battery voltage, when the device is ‘OFF,’ and the clamp diode conducts. If the maximum battery voltage spikes up to 20 V, the common-mode voltage at the input can be as high as 21.5 V. To produce a full-scale output of 4 V, a gain ×40 is used, adjust- able by ±5% to absorb the tolerance in the shunt. There is sufficient headroom to allow 10% overrange (to 4.4 V). The roughly triangular voltage across the sense resistor is averaged by a single-pole, low-pass filter, here set with a corner frequency = 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. A higher rate of attenuation can be obtained using a two-pole filter having fC = 20 Hz, as shown in Figure 12. Although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the single-pole filter. –IN GND A1 A2 +IN NC +VS OUT AD8200 5V OUTPUT INDUCTIVE LOAD POWER DEVICE 4 TERM SHUNT CLAMP DIODE BATTERY 14V COMMON C 127k 432k 50k FC = 1Hz – F (0.05 F FOR fC = 20Hz) C NC = NO CONNECT Figure 12. Illustration of 2-Pole Low-Pass Filtering DRIVING CHARGE REDISTRIBUTION A/D CONVERTERS When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection ( Q) can cause a signifi- cant deflection in the output voltage of the AD8200. Though generally of short duration, this deflection may persist until after the sample period of the ADC has expired, due to the relatively high open-loop output impedance of the AD8200. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high-frequency output impedance of the AD8200. For these applications, the output signal should be taken from the midpoint of the RLAG–CLAG combination as shown in Figure 13. Since the perturbations from the analog-to-digital converter are small, the output impedance of the AD8200 will appear to be low. The transient response will, therefore, have a time constant governed by the product of the two LAG components, CLAG × RLAG. For the values shown in Figure 13, this time constant is programmed at approximately 10 µs. Therefore, if samples are taken at several tens of microseconds or more, there will be negligible charge “stack-up.” +IN –IN 10k 10k AD8200 5V RLAG 1k CLAG 0.01 F PROCESSOR A/D A2 Figure 13. Recommended Circuit for Driving CMOS A /D 8-Lead SOIC Package (SO-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). |
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