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AD9203ARU Arkusz danych(PDF) 10 Page - Analog Devices |
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AD9203ARU Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 19 page REV. 0 AD9203 –10– INPUT AND REFERENCE OVERVIEW Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be –VREF. The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config- ure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the differ- ence of the voltages applied at the AINP and AINN input pins. Therefore, the equation, VCORE = AINP – AINN (1) defines the output of the differential input stage and provides the input to the A/D core. The voltage, VCORE, must satisfy the condition, –VREF ≤ V CORE ≤ VREF (2) where VREF is the voltage at the VREF pin. The actual span (AINP – AINN) of the ADC is ±VREF. While an infinite combination of AINP and AINN inputs exist that satisfy Equation 2, an additional limitation is placed on the inputs by the power supply voltages of the AD9203. The power supplies bound the valid operating range for AINP and AINN. The condition, AVSS – 0.3 V < AINP < AVDD + 0.3 V (3) AVSS – 0.3 V < AINN < AVDD + 0.3 V where AVSS is nominally 0 V and AVDD is nominally +3 V, defines this requirement. The range of valid inputs for AINP and AINN is any combination that satisfies both Equations 2 and 3. INTERNAL REFERENCE CONNECTION A comparator within the AD9203 will detect the potential of the VREF pin. If REFSENSE is grounded, the reference amplifier switch will connect to the resistor divider (see Figure 17). That will make VREF equal to 1 V. If resistors are placed between VREF, REFSENSE and ground, the switch will be connected to the REFSENSE position and the reference amplitude will de- pend on the external programming resistors (Figure 19). If REFSENSE is tied to VREF, the switch will also connect to REFSENSE and the reference voltage will be 0.5 V (Figure 18). REFTF and REFBF will drive the ADC conversion core and establish its maximum and minimum span. The range of the Table I. Modes Name Figure Number Advantages 1 V Differential Figure 26 with VREF Connected to REFSENSE Differential Modes Yield the Best Dynamic Performance 2 V Differential Figure 26 with REFSENSE Connected to AGND Differential Modes Yield the Best Dynamic Performance 1 V Single-Ended Figure 18 Video and Applications Requiring Clamping Require Single-Ended Inputs 2 V Single-Ended Figure 17 Video and Applications Requiring Clamping Require Single-Ended Inputs ADC will equal the twice voltage at the reference pin for both an internal or external reference. Figure 17 illustrates the input configured with a 1 V reference. This will set the single-ended input of the AD9203 in the 2 V span (2 × VREF). This example shows the AINN input is tied to the 1 V VREF. This will configure the AD9203 to accept a 2 V input centered around 1 V. ADC CORE + – 0.1 F 10 F AINP AINN VREF 0.5V REFTF REFBF REFSENSE 2V 0V AD9203 0.1 F 0.1 F 0.1 F 10 F 2V 1V LOGIC Figure 17. Internal Reference Set for a 2 V Span Figure 18 illustrates the input configured with a 0.5 V reference. This will set the single ended input of the ADC in a 1 V span (2 × VREF). The AINN input is tied to the 0.5 VREF. This will configure the AD9203 to accept a 1 V input centered around 0.5 V. ADC CORE + – LOGIC 0.1 F 10 F AINP AINN VREF 0.5V REFTF REFBF REFSENSE 1V 0V 0.1 F 1.75V 1.25V 0.1 F 10 F 0.1 F AD9203 Figure 18. Internal Reference Set for a 1 V Span |
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