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AD9300KQ Arkusz danych(PDF) 3 Page - Analog Devices |
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AD9300KQ Arkusz danych(HTML) 3 Page - Analog Devices |
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3 / 8 page  NOTES 11Permanent damage may occur if any one absolute maximum rating is exceeded. Functional operation is not implied, and device reliability may be impaired by exposure to higher-than-recommended voltages for extended periods of time. 12Measured at extremes of temperature range. 13Measured as slope of V OUT versus VIN with VIN = ± 1 V. 14Measured as worst deviation from endpoint fit with V IN = ± 1 V. 15Full Power Bandwidth (FPBW) based on Slew Rate (SR). FPBW = SR/2 π V PEAK 16Measured between 20% and 80% transition points of ±1 V output. 17T-Step = Sin2 × Step, when Step between 0 V and +700 mV points has 10% to 90% risetime = 125 ns. 18Measured with a pulse input having slew rate >250 V/ µs. 19Measured at output between 0.28 V dc and 1.0 V dc with V IN = 284 mV p-p at 3.58 MHz and 4.43 MHz. 10This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to remaining three channels. If selected channel is grounded through 75 Ω, value is approximately 6 dB higher. 11This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to one other channel. If selected channel is grounded through 75 Ω, value is approximately 6 dB higher. Minimum specification in ( ) applies to DIPs. 12Consult system timing diagram. 13Measured from address change to 90% point of –2 V to +2 V output LOW-to-HIGH transition. 14Measured from address change to 90% point of +2 V to –2 V output HIGH-to-LOW transition. 15Measured from 50% transition point of ENABLE input to 90% transition of 0 V to –2 V and 0 V to +2 V output. 16Measured from 50% transition point of ENABLE input to 10% transition of +2 V to 0 V and –2 V to 0 V output. 17Measured while switching between two grounded channels. 18Maximum power dissipation is a package-dependent parameter related to the following typical thermal impedances: 16-Pin Ceramic θ JA = 87°C/W; θJC = 25°C/W 20-Pin LCC θ JA = 74°C/W; θJC = 10°C/W 20-Pin PLCC θ JA = 71°C/W; θJC = 26°C/W Specifications subject to change without notice. REV. A –3– ABSOLUTE MAXIMUM RATINGS l Supply Voltages ( ±V S) . . . . . . . . . . . . . . . . . . . . . . . . . . ±16 V Analog Input Voltage Each Input (IN1 thru IN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 3.5 V Differential Voltage Between Any Two Inputs (IN1 thru IN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Digital Input Voltages (A0, A1, ENABLE) . . . –0.5 V to +5.5 V Output Current Sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0 mA Sourcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0 mA Operating Temperature Range AD9300KQ/KP . . . . . . . . . . . . . . . . . . . . . . . 0 °C to +70°C Storage Temperature Range . . . . . . . . . . . . –65 °C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175 °C Lead Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . +300 °C EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. Test Level II – 100% production tested at +25 °C, and sample tested at specified temperatures. Test Level III – Sample tested only. Test Level IV – Parameter is guaranteed by design and characterization testing. Test Level V – Parameter is a typical value only. Test Level VI – All devices are 100% production tested at +25 °C. 100% production tested at tempera- ture extremes for military temperature de- vices; sample tested at temperature extremes for commercial/industrial devices. AD9300 ORDERlNG GUlDE Temperature Package Device Range Description Option 1 AD9300KQ 0 °C to +70°C 16-Pin Cerdip, Commercial Q-16 AD9300TE/883B 2 –55 °C to +125°C 20-Pin LCC, Military Temperature E-20A AD9300TQ/883B 2 –55 °C to +125°C 16-Pin Cerdip, Military Temperature Q-16 AD9300KP 0 °C to +70°C 20-Pin PLCC, Commercial P-20A NOTES 1E = Ceramic Leadless Chip Carrier; P = Plastic Leaded Chip Carrier; Q = Cerdip. 2For specifications, refer to Analog Devices Military Products Databook. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. |
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