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AD9501JN Arkusz danych(PDF) 4 Page - Analog Devices |
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AD9501JN Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 12 page AD9501 REV. A –4– AD9501 PIN DESCRIPTIONS Pin No. Name Function 1+VS Positive voltage supply; nominally +5 V. 2 LATCH TTL/CMOS register control line. Logic HIGH latches input data D0–D7. Register is transparent for logic LOW. 3 TRIGGER TTL/CMOS-compatible input. Rising edge triggers the internal ramp generator, and begins the delay cycle. 4 RESET TTL/CMOS-compatible input. Logic HIGH resets the ramp voltage and OUTPUT. 5 DAC OUTPUT Output voltage of the internal digital-to-analog converter. 6CEXT Optional external capacitor connected to +VS; used with RSET and 8.5 pF internal capacitor to determine full-scale delay range (tDFS). 7RSET External resistor to ground, used to determine full-scale delay range (tDFS). 8 OFFSET ADJUST Normally connected to GROUND. Can be used to adjust minimum propagation delay (tPD); see Theory of Operation text. 9 GROUND Circuit ground return. 10 OUTPUT TTL-compatible delayed output pulse. 11 +VS Positive voltage supply; nominally +5 V. 12-19 D0–D7 TTL/CMOS-compatible inputs, used to set the programmed delay of the AD9501 delayed output. D0 is LSB and D7 is MSB. 20 GROUND Circuit ground return. AD9501 Equivalent Circuits WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9501 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. |
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