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AD9708 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD9708 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 16 page AD9708 –10– REV. B POWER DISSIPATION The power dissipation, PD, of the AD9708 is dependent on several factors, including: (1) AVDD and DVDD, the power supply voltages; (2) IOUTFS, the full-scale current output; (3) fCLOCK, the update rate; (4) and the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 19, and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input wave- form, fCLOCK, and digital supply DVDD. Figures 20 and 21 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5 V and DVDD = 3 V, respectively. Note, how IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3 V. APPLYING THE AD9708 Power and Grounding Considerations In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection placement and routing and supply bypassing and grounding. The evaluation board for the AD9708, which uses a four layer PC board, serves as a good example for the above mentioned considerations. The evaluation board provides an illustration of the recommended printed circuit board ground, power and signal plane layouts. Proper grounding and decoupling should be a primary objective in any high speed system. The AD9708 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Simi- larly, DVDD, the digital supply, should be decoupled to DCOM as close as physically as possible. For those applications requiring a single +5 V or +3 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 22. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR type electrolytic and tantalum capacitors. IOUTFS – mA 30 0 220 46 8 10 12 14 16 18 25 20 15 10 5 Figure 19. IAVDD vs. IOUTFS RATIO (fOUT/fCLK) 18 16 0 0.01 1 0.1 8 6 4 2 12 10 14 5MSPS 25MSPS 50MSPS 100MSPS 125MSPS Figure 20. IDVDD vs. Ratio @ DVDD = 5 V 100 F ELECT. 10-22 F TANT. 0.1 F CER. TTL/CMOS LOGIC CIRCUITS +5V OR +3V POWER SUPPLY FERRITE BEADS AVDD ACOM Figure 22. Differential LC Filter for Single +5 V or +3 V Applications Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9708. If properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current trans- port, etc. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. All analog ground pins of the DAC, reference and other analog components, should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal and the supply feeders. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some “free” capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduc- tion paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistor RATIO (fOUT/fCLK) 8 0 0.01 1 0.1 6 4 2 5MSPS 25MSPS 50MSPS 100MSPS 125MSPS Figure 21. IDVDD vs. Ratio @ DVDD = 3 V |
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Podobny opis - AD9708 |
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