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AD9698KN Arkusz danych(PDF) 5 Page - Analog Devices |
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AD9698KN Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 8 page AD9696/AD9698 –5– REV. B tH 50% 50% LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q TWO DIODES ABOVE GROUND LATCH COMPARE Q tPD tPD (E) VOS – MINIMUM SETUP TIME (Typically 1.7ns) – MINIMUM HOLD TIME (Typically 1.9ns) – INPUT TO OUTPUT DELAY – LATCH ENABLE TO OUTPUT DELAY t H tS t PD tPD (E) – MINIMUM LATCH ENABLE PULSE WIDTH (Typically 2.5ns) – INPUT OFFSET VOLTAGE – OVERDRIVE VOLTAGE VOS VOD t PW (E) VOD VIN tPW (E) tS AD9696/AD9698 Timing Diagram DIE LAYOUT AND MECHANICAL INFORMATION Die Dimensions AD9696 . . . . . . . . . . . . . 59 ×71×15 (±2) mils AD9698 . . . . . . . . . . . . 79 ×109×15 (±2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ×4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride THEORY OF OPERATION Refer to the block diagram of the AD9696/AD9698 compara- tors. The AD9696 and AD9698 TTL voltage comparator archi- tecture consists of five basic stages: input, latch, gain, level shift and output. Each stage is designed to provide optimal perfor- mance and make it easy to use the comparators. The input stage operates with either a single +5-volt supply, or with a +5-volt supply and a –5.2-volt supply. For optimum power efficiency, the remaining stages operate with only a single +5-volt supply. The input stage is an input differential pair without the customary emitter follower buffers. This configura- tion increases input bias currents but maximizes the input volt- age range. A latch stage allows the most recent output state to be retained as long as the latch input is held high. In this way, the input to the comparator can be changed without any change in the out- put state. As soon as the latch enable input is switched to LOW, the output changes to the new value dictated by the signal ap- plied to the input stage. The gain stage assures that even with small values of input volt- age, there will be sufficient levels applied to the following stages to cause the output to switch TTL states as required. A level shift stage between the gain stage and the TTL output stage guarantees that appropriate voltage levels are applied from the gain stage to the TTL output stage. Only the output stage uses TTL logic levels; this minimum use of TTL circuits maximizes speed and minimizes power con- sumption. The outputs are clamped with Schottky diodes to as- sure that the rising and falling edges of the output signal are closely matched. The AD9696 and AD9698 represent the state of the art in high speed TTL voltage comparators. Great care has been taken to optimize the propagation delay dispersion performance. This as- sures that the output delays will remain constant despite varying levels of input overdrive. This characteristic, along with closely matched rising and falling outputs, provides extremely consis- tent results at previously unattainable speeds. |
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