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AD9761ARS Arkusz danych(PDF) 4 Page - Analog Devices

Numer części AD9761ARS
Szczegółowy opis  Dual 10-Bit TxDAC??with 2x Interpolation Filters
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Strona internetowa  http://www.analog.com
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AD9761
–4–
REV. A
DIGITAL FILTER SPECIFICATIONS
Parameter
Min
Typ
Max
Units
MAXIMUM INPUT CLOCK RATE (fCLOCK)
40
MSPS
DIGITAL FILTER CHARACTERISTICS
Passband Width
1: 0.005 dB
0.2010
fOUT/fCLOCK
Passband Width: 0.01 dB
0.2025
fOUT/fCLOCK
Passband Width: 0.1 dB
0.2105
fOUT/fCLOCK
Passband Width: –3 dB
0.239
fOUT/fCLOCK
Linear Phase (FIR Implementation)
Stopband Rejection: 0.3 fCLOCK to 0.7 fCLOCK
–62.5
dB
Group Delay
2
32
Input Clock Cycles
Impulse Response Duration
3
–40 dB
28
Input Clock Cycles
–60 dB
40
Input Clock Cycles
NOTES
1Excludes SINX/X characteristic of DAC.
2Defined as the number of data clock cycles between impulse input and peak of output response.
355 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update.
(TMIN to TMAX, AVDD = +2.7 V to 5.5 V, DVDD = +2.7 V to 5.5 V, IOUTFS = 10 mA unless
otherwise noted)
FREQUENCY RESPONSE – DC to fCLOCK/2
0
–20
–120
0
0.5
0.1
0.2
0.3
0.4
–40
–60
–80
–100
Figure 2a. FIR Filter Frequency Response
TIME – Samples
1
0
040
5
10152025
30
35
0.9
0.6
0.4
0.2
0.1
0.8
0.7
0.5
0.3
–0.1
–0.2
–0.3
Figure 2b. FIR Filter Impulse Response
Table I. Integer Filter Coefficients for 43-Tap Halfband
FIR Filter
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(43)
1
H(2)
H(42)
0
H(3)
H(41)
–3
H(4)
H(40)
0
H(5)
H(39)
8
H(6)
H(38)
0
H(7)
H(37)
–16
H(8)
H(36)
0
H(9)
H(35)
29
H(10)
H(34)
0
H(11)
H(33)
–50
H(12)
H(32)
0
H(13)
H(31)
81
H(14)
H(30)
0
H(15)
H(29)
–131
H(16)
H(28)
0
H(17)
H(27)
216
H(18)
H(26)
0
H(19)
H(25)
–400
H(20)
H(24)
0
H(21)
H(23)
1264
H(22)
1998


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