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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD9850 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD9850 Arkusz danych(HTML) 10 Page - Analog Devices |
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10 / 19 page  AD9850 –10– REV. E Table II. Factory-Reserved Internal Test Control Codes Loading Format Factory-Reserved Codes Parallel 1) W0 = XXXXXX10 2) W0 = XXXXXX01 Serial 1) W32 = 1; W33 = 0 2) W32 = 0; W33 = 1 3) W32 = 1; W33 = 1 Table III. 8-Bit Parallel-Load Data/Control Word Functional Assignment Word data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] W0 Phase-b4 Phase-b3 Phase-b2 Phase-b1 Phase-b0 Power-Down Control Control (MSB) (LSB) W1 Freq-b31 Freq-b30 Freq-b29 Freq-b28 Freq-b27 Freq-b26 Freq-b25 Freq-b24 (MSB) W2 Freq-b23 Freq-b22 Freq-b21 Freq-b20 Freq-b19 Freq-b18 Freq-b17 Freq-b16 W3 Freq-b15 Freq-b14 Freq-b13 Freq-b12 Freq-b11 Freq-b10 Freq-b9 Freq-b8 W4 Freq-b7 Freq-b6 Freq-b5 Freq-b4 Freq-b3 Freq-b2 Freq-b1 Freq-b0 (LSB) tDS W0* W1 W2 W3 W4 tDH tWH tWL tCF VALID DATA OLD FREQ (PHASE) NEW FREQ (PHASE) *OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK DATA W CLK REF CLK COS OUT tDS DATA SETUP TIME 3.5ns tDH DATA HOLD TIME 3.5ns tWH W CLK HIGH 3.5ns tWL W CLK LOW 3.5ns tCD CLK DELAY AFTER FQ_UD 3.5ns tFH FQ UD HIGH 7.0ns tFL FQ UD LOW 7.0ns tFD FQ UD DELAY AFTER W CLK 7.0ns tCF OUTPUT LATENCY FROM FQ UD FREQUENCY CHANGE 18 CLOCK CYCLES PHASE CHANGE 13 CLOCK CYCLES SYMBOL DEFINITION MIN tCD tFD tFH tFL FQ UD Figure 18. Parallel-Load Frequency/Phase Update Timing Sequence |
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