ADC912A datasheet(2/16 Pages) AD

Numer części	ADC912A

Szczegółowy opis	CMOS Microprocessor-Compatible 12-Bit A/D Converter

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Producent	AD [Analog Devices]

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REV. B

–2–

ADC912A–SPECIFICATIONS (V

DD = +5 V

5%, VSS = –11.4 V to –15.75 V, VREFIN = –5 V, Analog Input O V to

10 V; External fCLK = 1.25 MHz; –40 C to +85 C applies to ADC912A/F unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

STATIC ACCURACY

Integral Nonlinearity

INL

–1

+1

LSB

Differential Nonlinearity

DNL

–1

+1

LSB

Offset Error

VZSE

VDD = +5 V, VSS = –12 V

–5

+5

LSB

Gain Error

GFSE

VDD = +5 V, VSS = –12 V

–6

+6

LSB

Full-Scale Tempco

1

TCGFS

5

15

ppm/

°C

ANALOG INPUT

Input Voltage Range

VIN

010

V

Input Current Range

IIN

03

mA

POWER SUPPLIES

Positive Supply Current

IDD

VDD = +5 V

2

57

mA

Negative Supply Current

ISS

VSS = –12 V

2

35

mA

Power Consumption

PDISS

VDD = +5 V

2, V

SS = –12 V

2

70

95

mW

Power Supply Rejection Ratio

PSRR+

∆VDD = ±5%, AIN = 10 V

1/2

4

LSB

PSRR–

∆V

SS =

±5%, A

IN = 10 V

1/2

4

LSB

DIGITAL INPUTS

Logic Input High Voltage

VINH

CS, RD, HBEN

2.4

V

Logic Input Low Voltage

VINL

CS, RD, HBEN

0.8

V

Logic Input Current

IIN

CS, RD, HBEN

±1

µA

Digital Input Capacitance

CIN

Digital Inputs,

CS, RD, HBEN, CLKIN

7

10

pF

DIGITAL OUTPUTS

Logic Input High Voltage

VOH

ISOURCE = 0.2 mA

4

V

Logic Input Low Voltage

VOL

ISINK = 1.6 mA

0.4

V

Three-State Output Leakage

IOZ

D11–D0/8

10

µA

Digital Input Capacitance

COUT

D11–D0/8

1

815

pF

DYNAMIC PERFORMANCE

Conversion Time

TC

fCLK = 1.25 MHz

3

Synchronous Clock

10.4

µs

Asynchronous Clock

10.4

11.2

µs

NOTES

1Guaranteed by design.

2Converter inactive;

CS, RD = High, A

IN = 10 V.

3See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25

°C. See Typical Performance

Characteristics for additional information.

Specifications subject to change without notice.

3k

CL

DGND

DBN

A. HIGH-Z TO V OH (t3)

AND VOL TO VOH (t6)

CL

3k

DGND

DBN

5V

B. HIGH-Z TO VOL (t3)

AND V OH TO VOL (t6)

Figure 3. Load Circuits for Access Time

3k

10pF

DGND

DBN

A. VOH TO HIGH-Z

10pF

3k

DGND

DBN

5V

B. VOL TO HIGH-Z

Figure 4. Load Circuits for Output Float Delay

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