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ADG466BR Arkusz danych(PDF) 8 Page - Analog Devices |
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ADG466BR Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 10 page ADG466/ADG467 –8– REV. A When a negative overvoltage is applied to the channel protector circuit, the PMOS transistor enters a saturated mode of opera- tion as the drain voltage exceeds VSS – VTP. See Figure 20 be- low. As in the case of the positive overvoltage, the other MOS devices are nonsaturated. NMOS PMOS NMOS VDD (+15V) VSS (–15V) VDD (+15V) NEGATIVE OVERVOLTAGE (–20V) VSS – VTP* (–13V) *VTP = PMOS THRESHOLD VOLTAGE (–2V) NEGATIVE OVERVOLTAGE (–20V) NON- SATURATED NON- SATURATED SATURATED Figure 20. Negative Overvoltage on the Channel Protector The channel protector is also functional when the supply rails are down (e.g., power failure) or momentarily unconnected (e.g., rack system). This is where the channel protector has an advantage over more conventional protection methods such as diode clamping (see Applications Information). When VDD and VSS equal 0 V, all transistors are off and the current is limited to subnano-ampere levels (see Figure 21). NMOS PMOS NMOS VDD (0V) VSS (0V) VDD (0V) POSITIVE OR NEGATIVE OVERVOLTAGE (0V) OFF OFF OFF Figure 21. Channel Protector Supplies Equal to Zero Volts TRENCH ISOLATION The MOS devices that make up the channel protector are iso- lated from each other by an oxide layer (trench) (see Figure 22). When the NMOS and PMOS devices are not electrically iso- lated from each other, there exists the possibility of “latch-up” caused by parasitic junctions between CMOS transistors. Latch- up is caused when P-N junctions that are normally reverse bi- ased become forward biased, causing large currents to flow, which can be destructive. CMOS devices are normally isolated from each other by Junc- tion Isolation. In Junction Isolation, the N and P wells of the CMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up proof circuit. VG VD P-CHANNEL P+ P+ VS N– VG VD N-CHANNEL N+ N+ VS P– T R E N C H T R E N C H T R E N C H BURIED OXIDE LAYER SUBSTRATE (BACKGATE) Figure 22. Trench Isolation |
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