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ADN2809XCP-RL Arkusz danych(PDF) 7 Page - Analog Devices

Numer części ADN2809XCP-RL
Szczegółowy opis  Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
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ADN2809
REV. PrB Oct. .2001
- 7 -
THEORY OF OPERATION
The ADN2809 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops which share a common control voltage.
A high speed delay- locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the vco,
tracks the low frequency components of input jitter. The initial
frequency of the vco is set by yet a third loop which compares
the vco frequency with the reference frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the vco by the fine tuning control.
The delay- and phase- loops together track the phase of the input
data signal. For example, when the clock lags input data, the
phase detector drives the vco to higher frequency, and also,
increases the delay through the phase shifter: these actions both
serve to reduce the phase error between the clock and data. The
faster clock picks up phase while the delayed data loses phase.
Since the loop filter is an integrator, the static phase error will be
driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second order
phase-locked loop, and this zero is placed in the feedback path
and thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Since this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay- and phase- loops together simultaneously provide
wide-band jitter accommodation and narrow-band jitter filtering.
The linearized block diagram in Figure 8 shows the jitter
transfer function , Z(s)/X(s), is a second order low pass
providing excellent filtering. Note the jitter transfer has no zero,
unlike an ordinary second order phase-locked loop. This means
that the main PLL loop has low jitter peaking, see Figure 9. This
makes this circuit ideal for signal regenerator applications where
jitter peaking in a cascade of regenerators can contribute to
hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wide-band jitter accommodation
since the jitter transfer function, Z(s)/X(s), provides the narrow-
band jitter filtering. See Figure 5 for a table of error transfer
bandwidths and jitter transfer bandwidths at the various data
rates.
The delay- and phase- loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to track
large jitter amplitudes with small phase error. In this case the
vco is frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the vco tuning range. A wider tuning
range gives larger accommodation of low frequency jitter. The
internal loop control voltage remains small for small phase
errors, so the phase shifter remains close to the center of its
range and thus contributes little to the low frequency jitter
accommodation.
At medium jitter frequencies, the gain and tuning range of the
vco are not large enough to track input jitter. In this case the vco
control voltage becomes large and saturates and the vco
frequency dwells at one or the other extreme of its tuning range.
The size of the vco tuning range, therefore has only a small
effect on the jitter accommodation. The delay-locked loop
control voltage is now larger, and so the phase shifter takes on
the burden of tracking the input jitter. The phase shifter range, in
UI, can be seen as a broad plateau on the jitter tolerance curve .
The phase shifter has a minimum range of 2UI at all data rates.
The gain of the loop integrator is small for high jitter
frequencies, so that larger phase differences are needed to make
the loop control voltage big enough to tune the range of the
phase shifter. Large phase errors at high jitter frequencies cannot
be tolerated. In this region the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small, and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by the
eye opening of the input data, the static phase error, and the
residual loop jitter generation. The jitter accommodation is
roughly 0.5UI in this region. The corner frequency between the
declining slope and the flat region is the closed loop bandwidth
of the delay-locked loop, which is roughly 3MHz for all data
rates.


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