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ADN2850 Arkusz danych(PDF) 11 Page - Analog Devices

Numer części ADN2850
Szczegółowy opis  Nonvolatile Memory, Dual 1024 Position Programmable Resistors
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Strona internetowa  http://www.analog.com
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REV. B
ADN2850
–11–
TERMINAL VOLTAGE OPERATING RANGE
The ADN2850 positive VDD and negative VSS power supply
defines the boundary conditions for proper two-terminal program-
mable resistance operation. Supply signals present on terminals W
and B that exceed VDD or VSS will be clamped by the internal
forward biased diodes (see Figure 7).
VSS
VDD
W
B
Figure 7. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the ADN2850 device is primarily used as a digital
ground reference that needs to be tied to the PCB’s common
ground. The digital input control signals to the ADN2850 must
be referenced to the device ground pin (GND), and satisfy the
logic level defined in the Specifications table of this data sheet.
An internal level shift circuit ensures that the common-mode
voltage range of the two terminals extends from VSS to VDD
regardless of the digital input level. In addition, there is no
polarity constraint on voltage across terminals W and B. The
magnitude of |VWB| is bounded by VDD – VSS.
Power-Up Sequence
Since diodes limit the voltage compliance at terminals B and W
(see Figure 7) it is important to power VDD/VSS first before apply-
ing any voltage to terminals B and W. Otherwise, the diode will be
forward biased such that VDD/VSS will be powered unintentionally.
For example, applying 5 V across VDD will cause the VDD terminal
to exhibit 4.3 V. Although it is not destructive to the device, it may
affect the rest of the user’s system. As a result, the ideal power-up
sequence is in the following order: GND, VDD, VSS, Digital Inputs,
and VB/W. The order of powering VB, VW, and Digital Inputs is not
important as long as they are powered after VDD/VSS.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on reset
remains effective, which retrieves EEMEM saved values to the
RDAC registers (see TPC 7).
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos-
sible with a minimum of conductor length. Ground paths should
have low resistance and low inductance. To minimize the digital
ground bounce, the digital signal ground reference can be joined
remotely to the analog ground terminal of the ADN2850.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01
µFto 0.1 µF disc or chip
ceramics capacitors. Low ESR 1
µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to minimize
any transient disturbance (see Figure 8).
ADN2850
C3
10 F
C4
10 F
+
+
C1
0.1 F
C2
0.1 F
VDD
VSS
GND
VDD
VSS
Figure 8. Power Supply Bypassing
RDAC STRUCTURE
The patent-pending RDAC contains a string of equal resistor
segments, with an array of analog switches, that act as the wiper
connection. The number of positions is the resolution of the
device. The ADN2850 has 1024 connection points, allowing it to
provide better than 0.1% setability resolution. Figure 9 shows an
equivalent structure of the connections between the two terminals
that make up one channel of the RDAC. The SWB will always be
ON, while one of the switches SW(0) to SW(2
N – 1) will be ON
one at a time depending on the resistance position decoded from
the data bits. Since the switch is not ideal, there is a 50
Ω wiper
resistance, RW. Wiper resistance is a function of supply voltage
and temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics if accurate
prediction of the output resistance is needed.
SW(1)
SW(0)
SWB
B
RS
RS
SW(2N–1)
W
SW(2N– 2)
RDAC
WIPER
REGISTER
AND
DECODER
RS = RWB /2
N
RS
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
Figure 9. Equivalent RDAC Structure
Table VII. Nominal Individual Segment Resistor Values
Device Resolution
25 k
250 k
1024-Step
24.4
244
CALCULATING THE PROGRAMMABLE RESISTANCE
The nominal full-scale resistance of the RDAC between terminals
W and B, RWB_FS, is available with 25 k
Ω and 250 kΩ with 1024
positions (10-bit resolution). The final digits of the part number
determine the nominal resistance value, e.g., 25 k
Ω = 25 and
250 k
Ω = 250.
The 10-bit data-word in the RDAC latch is decoded to select one
of the 1024 possible settings. The following discussion describes
the calculation of resistance RWB(D) at different codes of a 25 k
part. The wiper’s first connection starts at the B terminal for
data 000H. RWB(0) is 50
Ω because of the wiper resistance and it
is independent of the full-scale resistance. The second connection
is the first tap point where RWB(1) becomes 24.4
Ω + 50 = 74.4 Ω


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