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ADN2850BCP250 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADN2850BCP250 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 20 page REV. B –6– ADN2850 VSS GND V1 V2 PR WP VDD 16 ADN2850BCP CHIP SCALE PACKAGE 15 14 13 12 11 10 9 8 7 6 5 SDO 4 3 2 1 ADN2850BCP PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1SDO Serial Data Output Pin. Open-Drain output requires external pull-up resistor. CMD_9 and CMD_10 activate the SDO output. See Instruction Operation Truth Table (Table II). Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. 2GND Ground Pin, logic ground reference 3VSS Negative Supply. Connect to zero volts for single-supply applications. 4V1 Log Output Voltage 1 generated from internal diode configured transistor 5W1Wiper terminal of RDAC1 ADDR (RDAC1) = 0H. 6B1B terminal of RDAC1 7B2B terminal of RDAC2 8W2Wiper terminal of RDAC2. ADDR (RDAC2) = 1H. 9V2 Log Output Voltage 2 generated from internal diode configured transistor 10 VDD Positive Power Supply Pin 11 WP Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and CMD_1 and CMD_8 will refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. 12 PR Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user ( PR is activated at the logic high transition). 13 CS Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. 14 RDY Ready. Active high open-drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR. 15 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. 16 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. TOP VIEW (Not To Scale) 1 2 3 4 5 6 7 8 SDI SDO GND V1 VSS W1 ADN2850BRU CLK B1 16 15 14 13 12 11 10 9 CS PR WP VDD V2 W2 B2 RDY ADN2850BRU PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. 2 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. 3SDO Serial Data Output Pin. Open-drain out put requires external pull-up resistor. CMD_9 and CMD_10 activate the SDO output. See Instruction Operation Truth Table (Table II). Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. 4GND Ground Pin, logic ground reference 5VSS Negative Supply. Connect to zero volts for single-supply applications. 6V1 Log Output Voltage 1 generated from internal diode configured transistor 7W1Wiper terminal of RDAC1. ADDR (RDAC1) = 0H. 8B1B terminal of RDAC1 9B2B terminal of RDAC2 10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 1H. 11 V2 Log Output Voltage 2 generated from internal diode configured transistor 12 VDD Positive Power Supply Pin 13 WP Write Protect Pin. When active low, WP prevents any changes to the present contents except PR and CMD_1 and CMD_8 will refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. 14 PR Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user ( PR is activated at the logic high transition). 15 CS Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. 16 RDY Ready. Active high open-drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR. PIN CONFIGURATIONS |
Podobny numer części - ADN2850BCP250 |
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Podobny opis - ADN2850BCP250 |
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