REV. 0

ADP3163

–6–

Table II. Output Voltage vs. VID Code

VID4

VID3

VID2

VID1

VID0

11111No CPU

11110

1.100 V

11101

1.125 V

11100

1.150 V

11011

1.175 V

11010

1.200 V

11001

1.225 V

11000

1.250 V

10111

1.275 V

10110

1.300 V

10101

1.325 V

10100

1.350 V

10011

1.375 V

10010

1.400 V

10001

1.425 V

10000

1.450 V

01111

1.475 V

01110

1.500 V

01101

1.525 V

01100

1.550 V

01011

1.575 V

01010

1.600 V

01001

1.625 V

01000

1.650 V

00111

1.675 V

00110

1.700 V

00101

1.725 V

00100

1.750 V

00011

1.775 V

00010

1.800 V

00001

1.825 V

00000

1.850 V

THEORY OF OPERATION

The ADP3163 combines a current-mode, fixed frequency PWM

controller with multiphase logic outputs for use in a 2- or 3-phase

synchronous buck power converter. Multiphase operation is

important for switching the high currents required by high

performance microprocessors. Handling the high current in a

single-phase converter would place unreasonable requirements on

the power components such as inductor wire size and MOSFET

ON-resistance and thermal dissipation. The ADP3163’s high-side

current sensing topology ensures that the load currents are

balanced in each phase, such that no single phase has to carry

more than it’s share of the power. An additional benefit of high

side current sensing over output current sensing is that the

average current through the sense resistor is reduced by the duty

cycle of the converter allowing the use of a lower power, lower

cost resistor. The outputs of the ADP3163 are logic drivers

only and are not intended to directly drive external power

MOSFETs. Instead, the ADP3163 should be paired with driv-

ers such as the ADP3413 or ADP3414.

The frequency of the ADP3163 is set by an external capacitor

connected to the CT pin. The phase relationship and number of

active output phases is determined by the state of the phase

control (PC) pin as shown in Table I. The error amplifier and

current sense comparator control the duty cycle of the PWM

outputs to maintain regulation. The maximum duty cycle per

phase is inherently limited to 50% for 2-phase operation and

33% for 3-phase operation. While one phase is on, all other

phases remain off. In no case can more than one output be high

at any time.

Output Voltage Sensing

The output voltage is sensed at the FB pin allowing for remote

sensing. To maintain the accuracy of the remote sensing, the

GND pin should also be connected close to the load. A voltage

voltage and a programmable reference voltage. The reference

voltage is programmed between 1.1 V and 1.85 V by an internal

5-bit DAC, which reads the code at the voltage identification

(VID) pins. (Refer to Table II for the output voltage versus VID

pin code information.)

Active Voltage Positioning

The ADP3163 uses Analog Devices Optimal Positioning Tech-

nology (ADOPT), a unique supplemental regulation technique

that uses active voltage positioning and provides optimal com-

pensation for load transients. When implemented, ADOPT

adjusts the output voltage as a function of the load current, so

that it is always optimally positioned for a load transient.

Standard (passive) voltage positioning has poor dynamic perfor-

mance, rendering it ineffective under the stringent repetitive

transient conditions required by high performance processors.

ADOPT, however, provides optimal bandwidth for transient

response that yields optimal load transient response with the

minimum number of output capacitors.

Reference Output

A 3.0 V reference is available on the ADP3163. This reference

is normally used to set the voltage positioning accurately using a

resistor divider to the COMP pin. In addition, the reference can

be used for other functions such as generating a regulated volt-

age with an external amplifier. The reference is bypassed with

a 1 nF capacitor to ground. It is not intended to supply large

capacitive loads, and it should not be used to provide more than

300

µA of output current.

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),

the voltage-error amplifier and the current comparator are the

main control elements. The voltage at the CT pin of the oscilla-

tor ramps between 0 V and 3 V. When that voltage reaches 3 V,

the oscillator sets the driver logic, which sets PWM1 high. Dur-

ing the ON time of Phase 1, the driver IC turns on the Phase 1

high-side MOSFET. The CS+ and CS– pins monitor the current

through the sense resistor that feeds all the high side MOSFETs.

When the voltage between the two pins exceeds the threshold

level, the driver logic is reset and the PWM1 output goes low. This

signals the driver IC to turn off the Phase 1 high side MOSFET

and turn on the Phase 1 low side MOSFET. On the next cycle

of the oscillator, the driver logic toggles and sets PWM2 high.

On each following cycle of the oscillator, the driver logic cycles

between each of the active PWM outputs based on the logic

state of the PC pin. In each case, the current comparator resets

the PWM output low when its threshold is reached. As the load

current increases, the output voltage starts to decrease. This

turn leads to an increase in the current comparator threshold,

thus programming more load current to be delivered so that

voltage regulation is maintained.