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ADP3413JR Arkusz danych(PDF) 1 Page - Analog Devices

Numer części ADP3413JR
Szczegółowy opis  Dual Bootstrapped MOSFET Driver with Output Disable
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ADP3413JR Arkusz danych(HTML) 1 Page - Analog Devices

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
ADP3413
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
Dual Bootstrapped MOSFET Driver
with Output Disable
FUNCTIONAL BLOCK DIAGRAM
IN
VCC
OVERLAP
PROTECTION
CIRCUIT
BST
DRVH
SW
DRVL
PGND
OD 3
ADP3413
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Pulse-by-Pulse Disable Control
APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
GENERAL DESCRIPTION
The ADP3413 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped, and is designed to handle the high-voltage
slew rate associated with “floating” high-side gate drivers.
The ADP3413 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
The
OD pin provides high speed control to quickly turn off
both gate drives.
The ADP3413 is specified over the commercial temperature
range of 0
°C to 70°C and is available in an 8-lead SOIC package.
IN
VCC
ADP3413
BST
DRVH
SW
DRVL
PGND
DELAY
1V
+1V
12V
CBST
7V
Q1
Q2
OD 3
D1
Figure 1. General Application Circuit


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