REV. 0

ADP3422

–7–

Pin No.

Mnemonic

Function

13

DPRSLP

Deeper Sleep Mode (active high). This is a digital input pin coming from a system signal corresponding to

Deeper Sleep mode of the CPU operation in its active high state. It is used to initiate a blanking period

for the PWRGD signal (to disable its response to a pending dynamic core voltage change according to the

VID code) whenever a signal transition occurs.

14

PWRGD

Power Good (active high). This is an open drain output pin which, via the assistance of an external

pull-up resistor, indicates that the core voltage is within the specified tolerance of the VID programmed

value or else in a VID transition state as indicated by a recent state transition of either the

BOM or

DPRSLP pins. PWRGD is deactivated (pulled low) when the IC is disabled or in UVLO mode or

soft-start. The open drain output allows external ORing with other open drain/collector power-

good indicators.

15

SD

Shutdown (active low). This is a digital input pin coming from a system signal which, in its active

state, shuts down the IC operation, placing the IC in its lowest quiescent current state for maximum

power savings.

16

CLAMP

Clamp (active high). This is an open drain output pin which, via the assistance of an external pull-up

resistor, indicates that the core voltage should be clamped for its protection. To allow the highest

level of protection, the CLAMP signal is developed using both a redundant reference and a re-

dundant feedback path with respect to those of the main regulation loop. It is also latched. In a

preferred and more conservative configuration, the core voltage is clamped by an external FET.

The initial protection function is served when it is activated by detection of either an overvoltage or a

reverse-voltage condition on the COREFB pin. A backup protection function due to loss of the

latched signal at IC power-off is served by connecting the pull-up resistor to a system “ALWAYS”

regulator output (e.g., V5_ALWAYS). If the external FET is used, this implementation will keep the

core voltage clamped until the ADP3422 has power reapplied, thus keeping protection for the

CPU even after a hard-failure power-down and restart (e.g., a shorted top FET).

17

DRVLSD

Drive-Low Shutdown (active low). This is a digital output pin which, in its active state, indicates that

the lower FET of the core VR should be disabled. In the suggested application schematic this pin is

directly connected to the pin of the same name on the ADP3415 or other driver IC. The pin is normally

asserted in the light load condition, but its assertion will be deactivated by the consideration of a

number of dynamic conditions where operation of the lower FET may be needed.

18

SWFB

Switched Node Feedback. This is a high-impedance analog input pin that is used to allow the

ON-time noise blanking function to terminate earlier than its internally preset time by its indication

that the turn-ON of the upper FET has occurred. A resistor must be inserted between the pin and the

switched node of the core VR so that the input can be clamped (at ~7V) and is not exposed to

high voltage. This pin can also be shorted to ground if the need for this speed enhancement is

deemed unnecessary.

19

SS

Soft Start. This is an analog I/O pin whose output is a controlled current source used to charge or

discharge an external grounded capacitor and whose input is the detected voltage that is indicative of

elapsed time. The pin controls the soft start time of the IC as well as the hiccup cycle time during

short circuit. Hiccup operation is a feature that was added to reduce short circuit power dissipation by

more than an order of magnitude, while still allowing an automatic restart when the short is removed.

20

COREFB

Core Feedback. This is a high-impedance analog input pin that is used to monitor the output voltage

for setting the proper state of the PWRGD and CLAMP pins. It is generally recommended to

RC-filter the noise from the monitored core voltage, as suggested by the application schematic.

21

DACOUT

VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output

voltage regulation.

22

GND

Ground

23

OUT

Driver Command Output Signal. This is a digital output pin which is used to command the state of the

switched node via the driver. It should be connected to the IN pin of the ADP3415 or similar driver.

24

VCC

Power Supply