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ADSP-21MSP59 Arkusz danych(PDF) 5 Page - Analog Devices |
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ADSP-21MSP59 Arkusz danych(HTML) 5 Page - Analog Devices |
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5 / 40 page  ADSP-21msp58/59 REV. 0 –5– Table II. Interrupt Priority & Interrupt Vector Addresses Interrupt Vector Source of Interrupt Address (Hex) Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Powerdown (Nonmaskable) 002C IRQ2 0004 HIP Write 0008 HIP Read 000C SPORT0 Transmit 0010 SPORT0 Receive 0014 Analog Interface Transmit 0018 Analog Interface Receive 001C SPORT1 Transmit or (IRQ1) 0020 SPORT1 Receive or (IRQ0) 0024 Timer 0028 (Lowest Priority) Interrupts can be masked or unmasked with the IMASK regis- ter. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The powerdown interrupt is non-maskable. The interrupt control register, ICNTL, allows the external in- terrupts to be set as either edge- or level-sensitive. Interrupt ser- vice routines can either be nested (with higher priority interrupts taking precedence) or be processed sequentially (with only one interrupt service active at a time). The interrupt force and clear register, IFC, is a write-only regis- ter used to force an interrupt or clear a pending edge-sensitive interrupt. On-chip stacks preserve the processor status and are automati- cally maintained during interrupt handling. The stack is twelve levels deep to allow interrupt nesting. Register bit values shown in Figure 2 are the default bit values after reset. If no values are shown, the bits are indeterminate at reset. Reserved bits are shown in gray; these bits should always be written with zeros. 00 00000 00000 0000 15 14 13 12 11 10 98765 4 3 21 0 Timer SPORT1 Receive or IRQ0 SPORT1 Transmit or IRQ1 Analog Receive Analog Transmit SPORT0 Receive SPORT0 Transmit IRQ2 1 = enable, 0 = disable INTERRUPT CLEAR IRQ2 SPORT0 Transmit SPORT0 Receive Analog Transmit Analog Receive SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer INTERRUPT FORCE IFC 0 00000 0000 98765 4 3 21 0 Timer IRQ0 or SPORT1 Receive IRQ1 or SPORT1 Transmit Analog Receive Analog Transmit 1 = enable, 0 = disable IRQ2 HIP Write HIP Read SPORT0 Transmit SPORT0 Receive IMASK 4 3 210 0 ICNTL IRQ0 Sensitivity IRQ1 Sensitivity IRQ2 Sensitivity Interrupt Nesting 1 = edge 0 = level 1 = enable, 0 = disable Figure 2. Interrupt Registers The following instructions allow global enable or disable servic- ing of the interrupts (including powerdown), regardless of the state of IMASK. Disabling the interrupts does not affect autobuffering. ENA INTS; DIS INTS; Interrupt servicing is enabled on processor reset. System Interface Figure 3 shows a basic system configuration with the ADSP- 21msp58/59, two serial devices, a host processor, a boot EPROM, optional external program and data memories, and an analog interface. Up to 15K words of data memory and 16K words of program memory can be supported. Programmable wait state generation allows the processor to interface easily to slow memories. The ADSP-21msp58/59 also provides one ex- ternal interrupt and two serial ports or three external interrupts and one serial port. Clock Signals The ADSP-21msp58/59 CLKIN input may be driven by a crys- tal or by a TTL-compatible external clock signal. The CLKIN input may not be halted, changed in frequency during operation, or operated at any frequency other the one specified. Operating the ADSP-21msp58/59 at any other fre- quency changes the analog performance, which is not tested or supported. If an external clock is used, it should be a TTL-compatible sig- nal running at half the instruction rate. The signal should be connected to the processor’s CLKIN input; in this case, the XTAL input must be left unconnected. The ADSP-21msp58/59 uses an input clock with a frequency equal to half the instruction rate; a 13 MHz input clock yields a 38.46 ns processor cycle (which is equivalent to 26 MHz). Nor- mally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. The |
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