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ADT7318ARQ Arkusz danych(PDF) 4 Page - Analog Devices |
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ADT7318ARQ Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 32 page –4– REV. PrN PRELIMINARY TECHNICAL DATA ADT7316/7317/7318 DAC AC CHARACTERISTICS1 (VDD = +2.7V to +5.5 V; RL=4k7Ω to GND; CL=200pF to GND; 4K7 Ω to V DD; All specifications TMIN to TMAX unless otherwise noted.) Parameter2 Min Typ @ 25°C M a x Units Conditions/Comments Output Voltage Settling Time VREF=VDD=+5V ADT7318 6 8 µ s 1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex) ADT7317 7 9 µ s 1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex) ADT7316 8 1 0 µ s 1/4 Scale to 3/4 Scale change (400 Hex to C00 Hex) Slew Rate 0.7 V/µs Major-Code Change Glitch Energy 1 2 nV-s 1 LSB change around major carry. Digital Feedthrough 0.5 nV-s Digital Crosstalk 1 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 k H z VREF=2V±0.1Vpp Total Harmonic Distortion -70 d B VREF=2.5V±0.1Vpp. Frequency=10kHz. NOTES 1Guaranteed by Design and Characterization, not production tested 2See Terminology Specifications subject to change without notice. t1 t4 t2 t 3 t5 SC L SD A DA T A IN SD A DA T A O U T t6 Figure 1. Diagram for I2C Bus Timing IDD (Normal Mode) 13 0.85 1.3 m A VIH = VDD and VIL = GND IDD (Power Down Mode) 1 3 µ A VDD = +4.5V to +5.5V, VIH=VDD and VIL=GND 0.5 1 µ A VDD = +2.7V to +3.6V, VIH=VDD and VIL=GND Power Dissipation tbd tbd tbd µ W VDD = +2.7 V. Using Normal Mode tbd tbd tbd µ W VDD = +2.7 V. Using Shutdown Mode Notes: 1 Temperature ranges are as follows: A Version: -40°C to +125°C. 2 See Terminology. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255) 5 See Terminology. 6 Guaranteed by Design and Characterization, not production tested 7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V REF=VDD , "Offset plus Gain" Error must be positive. 8 The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I2C specification. Switching off the input filters improves the transfer rate but has a negative affect on the EMC behaviour of the part. 9 Guaranteed by design. Not tested in production. 10 Guaranteed by design and characterization, not production tested. 11 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 12 Measured with the load circuit of Figure 3. 13 I DD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded. Specifications subject to change without notice. |
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