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ADSP-2111BS-52 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADSP-2111BS-52 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 64 page ADSP-21xx –6– REV. B of the ADSP-2111. The two status registers provide status information to both the ADSP-2111 and the host processor. HSR7 contains a software reset bit which can be set by both the ADSP-2111 and the host. HIP transfers can be managed using either interrupts or polling. The HIP generates an interrupt whenever an HDR register receives data from a host processor write. It also generates an interrupt when the host processor has performed a successful read of any HDR. The read/write status of the HDRs is also stored in the HSR registers. The HMASK register bits can be used to mask the generation of read or write interrupts from individual HDR registers. Bits in the IMASK register enable and disable all HIP read interrupts or all HIP write interrupts. So, for example, a write to HDR4 will cause an interrupt only if both the HDR4 Write bit in HMASK and the HIP Write interrupt enable bit in IMASK are set. The HIP provides a second method of booting the ADSP-2111 in which the host processor loads instructions into the HIP. The ADSP-2111 automatically transfers the data, in this case opcodes, to internal program memory. The BMODE pin determines whether the ADSP-2111 boots from the host processor through the HIP or from external EPROM over the data bus. Interrupts The ADSP-21xx’s interrupt controller lets the processor respond to interrupts with a minimum of overhead. Up to three external interrupt input pins, IRQ0, IRQ1, and IRQ2, are provided. IRQ2 is always available as a dedicated pin; IRQ1 and IRQ0 may be alternately configured as part of Serial Port 1. The ADSP-21xx also supports internal interrupts from the timer, the serial ports, and the host interface port (on the ADSP-2111). The interrupts are internally prioritized and individually maskable (except for RESET which is non-maskable). The IRQx input pins can be programmed for either level- or edge- sensitivity. The interrupt priorities for each ADSP-21xx processor are shown in Table III. The ADSP-21xx uses a vectored interrupt scheme: when an interrupt is acknowledged, the processor shifts program control to the interrupt vector address corresponding to the interrupt received. Interrupts can be optionally nested so that a higher priority interrupt can preempt the currently executing interrupt service routine. Each interrupt vector location is four instruc- tions in length so that simple service routines can be coded entirely in this space. Longer service routines require an additional JUMP or CALL instruction. Individual interrupt requests are logically ANDed with the bits in the IMASK register; the highest-priority unmasked interrupt is then selected. The interrupt control register, ICNTL, allows the external interrupts to be set as either edge- or level-sensitive. Depending on bit 4 in ICNTL, interrupt service routines can either be nested (with higher priority interrupts taking precedence) or be processed sequentially (with only one interrupt service active at a time). Flexible Framing—The SPORTs have independent framing for the transmit and receive functions; each function can run in a frameless mode or with frame synchronization signals inter- nally generated or externally generated; frame sync signals may be active high or inverted, with either of two pulse widths and timings. Different Word Lengths—Each SPORT supports serial data word lengths from 3 to 16 bits. Companding in Hardware—Each SPORT provides optional A-law and µ-law companding according to CCITT recommen- dation G.711. Flexible Interrupt Scheme—Receive and transmit functions can generate a unique interrupt upon completion of a data word transfer. Autobuffering with Single-Cycle Overhead—Each SPORT can automatically receive or transmit the contents of an entire circular data buffer with only one overhead cycle per data word; an interrupt is generated after the transfer of the entire buffer is completed. Multichannel Capability (SPORT0 Only)—SPORT0 provides a multichannel interface to selectively receive or transmit a 24-word or 32-word, time-division multiplexed serial bit stream; this feature is especially useful for T1 or CEPT interfaces, or as a network communication scheme for multiple processors. (Note that the ADSP-2105 includes only SPORT1, not SPORT0, and thus does not offer multichannel operation.) Alternate Configuration—SPORT1 can be alternatively configured as two external interrupt inputs (IRQ0, IRQ1) and the Flag In and Flag Out signals (FI, FO). Host Interface Port (ADSP-2111) The ADSP-2111 includes a Host Interface Port (HIP), a parallel I/O port that allows easy connection to a host processor. Through the HIP, the ADSP-2111 can be accessed by the host processor as a memory-mapped peripheral. The host interface port can be thought of as an area of dual-ported memory, or mailbox registers, that allows communication between the computational core of the ADSP-2111 and the host computer. The host interface port is completely asynchronous. The host processor can write data into the HIP while the ADSP-2111 is operating at full speed. Three pins configure the HIP for operation with different types of host processors. The HSIZE pin configures HIP for 8- or 16- bit communication with the host processor. HMD0 configures the bus strobes, selecting either separate read and write strobes or a single read/write select and a host data strobe. HMD1 selects either separate address (3-bit) and data (16-bit) buses or a multiplexed 16-bit address/data bus with address latch enable. Tying these pins to appropriate values configures the ADSP- 2111 for straight-wire interface to a variety of industry-standard microprocessors and microcomputers. The HIP contains six data registers (HDR5-0) and two status registers (HSR7-6) with an associated HMASK register for masking interrupts from individual HIP data registers. The HIP data registers are memory-mapped in the internal data memory |
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