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ADXL05JH Arkusz danych(PDF) 17 Page - Analog Devices |
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ADXL05JH Arkusz danych(HTML) 17 Page - Analog Devices |
17 / 20 page ADXL05 –17– REV. B 10 0% 100 90 200µs 2V 500mV Figure 33. Top Trace: Voltage at Pin 1; Bottom Trace: Buffer Output With R1 = R3 = 100 k Ω, C F = 0.01 µF COMPONENT SELECTION LOAD DRIVE CAPABILITIES OF THE VPR AND BUFFER OUTPUTS The VPR and the buffer amplifier outputs are both capable of driving a load to voltage levels approaching that of the supply rail. However, both outputs are limited in how much current they can supply, affecting component selection. VPR Output The VPR pin has the ability to source current up to 500 µA but only has a sinking capability of 30 µA which limits its ability to drive loads. It is recommended that the buffer amplifier be used in most applications, to avoid loading down VPR. In standard ±5 g applications, the resistor R1 from V PR to VIN– is recom- mended to have a value greater than 20 k Ω to reduce loading effects. Capacitive loading of the VPR pin should be minimized. A load capacitance between the VPR pin and common will introduce an offset of approximately 1 mV for every 10 pF of load. The VPR pin may be used to directly drive an A/D input or other source as long as these sensitivities are taken into account. It is always preferable to drive A/D converters or other sources using the buffer amplifier (or an external op amp) instead of the VPR pin. Buffer Amplifier Output The buffer output can drive a load to within 0.25 V of either power supply rail and is capable of driving 1000 pF capacitive loads. Note that a capacitance connected across the buffer feedback resistor for low-pass filtering does not appear as a capacitive load to the buffer. The buffer amplifier is limited to sourcing or sinking a maximum of 100 µA. Component values for the resistor network should be selected to ensure that the buffer amplifier can drive the filter under worst case transient conditions. Self-Test Function The digital self-test input is compatible with both CMOS and TTL signals. A Logic “l” applied to the self-test (ST) input will cause an electrostatic force to be applied to the sensor which will cause it to deflect to the approximate negative full-scale output of the device. Accordingly, a correctly functioning accel- erometer will respond by initiating an approximate –1 volt so that the duty cycle is correct when the pulse is re-inverted again by transistor, Q2, which cycles the accelerometer’s supply voltage on and off. ADXL05 VPR VIN– VOUT 58 10 R3 9 R1 CF VOUT FROM µP OR FIGURE 1b Q1 10k Ω 2N3906 0.1µF BUFFER +5V 1 2N2222 100k Ω 10k Ω Q2 Figure 31. Basic Power Cycling Circuit Figures 32 and 33 show typical waveforms of the accelerometer being operated with a 10% duty cycle: 1 ms on, 9 ms off. This reduces the average current consumption of the accelerometer from 8 mA to 800 µA, providing a power reduction of 90%. The µP should sample acceleration during the interval between the time the 0 g level has stabilized ( ≈ 400 µs using a 0.022 µF demod cap) and the end of the pulse duration. The measure- ment bandwidth of a power-cycled circuit will be set by the clock pulse rate and duty cycle. In this example, 1 sample can be taken every 10 ms which is 100 samples per second or 100 Hz. As defined by the “Nyquist criteria,” the best case measure- ment bandwidth is FS/2 or half the clock frequency. Therefore 50 Hz signals can be processed if adequate filtering is provided. 10 0% 200µs 2V 1V 100 90 Figure 32. Top Trace: Voltage at Pin 1; Bottom Trace: Output at VPR Higher measurement bandwidths can be achieved by reducing the size of the demodulation capacitor below 0.022 µF and in- creasing the pulse frequency. A 0.01 µF capacitor was con- nected across the feedback resistor of the ADXL05 buffer to improve its transient characteristics. The optimum value for this capacitor will change with buffer gain and the cycling pulse rate. For more details, refer to application note AN-378. |
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