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ADXL202AQC Datasheet(Arkusz danych) 6 Page - Analog Devices

Numer części ADXL202AQC
Szczegółowy opis  Low Cost -2 g/-10 g Dual Axis iMEMS Accelerometers with Digital Output
Pobierz  11 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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ADXL202/ADXL210
REV. B
–6–
DEFINITIONS
T1
Length of the “on” portion of the cycle.
T2
Length of the total cycle.
Duty Cycle
Ratio of the “on” time (T1) of the cycle to the total
cycle (T2). Defined as T1/T2 for the ADXL202/
ADXL210.
Pulsewidth
Time period of the “on” pulse. Defined as T1 for
the ADXL202/ADXL210.
THEORY OF OPERATION
The ADXL202/ADXL210 are complete dual axis acceleration
measurement systems on a single monolithic IC. They contain a
polysilicon surface-micromachined sensor and signal condition-
ing circuitry to implement an open loop acceleration measure-
ment architecture. For each axis, an output circuit converts the
analog signal to a duty cycle modulated (DCM) digital signal
that can be decoded with a counter/timer port on a micropro-
cessor. The ADXL202/ADXL210 are capable of measuring
both positive and negative accelerations to a maximum level of
±2 g or ±10 g. The accelerometer measures static acceleration
forces such as gravity, allowing it to be used as a tilt sensor.
The sensor is a surface micromachined polysilicon structure
built on top of the silicon wafer. Polysilicon springs suspend the
structure over the surface of the wafer and provide a resistance
against acceleration forces. Deflection of the structure is mea-
sured using a differential capacitor that consists of independent
fixed plates and central plates attached to the moving mass. The
fixed plates are driven by 180
° out of phase square waves. An
acceleration will deflect the beam and unbalance the differential
capacitor, resulting in an output square wave whose amplitude
is proportional to acceleration. Phase sensitive demodulation
techniques are then used to rectify the signal and determine the
direction of the acceleration.
The output of the demodulator drives a duty cycle modulator
(DCM) stage through a 32 k
Ω resistor. At this point a pin is
available on each channel to allow the user to set the signal
bandwidth of the device by adding a capacitor. This filtering
improves measurement resolution and helps prevent aliasing.
After being low-pass filtered, the analog signal is converted to a
duty cycle modulated signal by the DCM stage. A single resistor
sets the period for a complete cycle (T2), which can be set be-
tween 0.5 ms and 10 ms (see Figure 12). A 0 g acceleration
produces a nominally 50% duty cycle. The acceleration signal
can be determined by measuring the length of the T1 and T2
pulses with a counter/timer or with a polling loop using a low
cost microcontroller.
An analog output voltage can be obtained either by buffering the
signal from the XFILT and YFILT pin, or by passing the duty cycle
signal through an RC filter to reconstruct the dc value.
The ADXL202/ADXL210 will operate with supply voltages as
low as 3.0 V or as high as 5.25 V.
A(
g) = (T1/T2 – 0.5)/12.5%
0
g = 50% DUTY CYCLE
T2(s) = RSET( )/125M
T2
T1
Figure 12. Typical Output Duty Cycle
APPLICATIONS
POWER SUPPLY DECOUPLING
For most applications a single 0.1
µF capacitor, C
DC, will ad-
equately decouple the accelerometer from signal and noise on
the power supply. However, in some cases, especially where digital
devices such as microcontrollers share the same power supply, digi-
tal noise on the supply may cause interference on the ADXL202/
ADXL210 output. This is often observed as a slowly undulating
fluctuation of voltage at XFILT and YFILT. If additional decou-
pling is needed, a 100
Ω (or smaller) resistor or ferrite beads,
may be inserted in the ADXL202/ADXL210’s supply line.
DESIGN PROCEDURE FOR THE ADXL202/ADXL210
The design procedure for using the ADXL202/ADXL210 with a
duty cycle output involves selecting a duty cycle period and a
filter capacitor. A proper design will take into account the appli-
cation requirements for bandwidth, signal resolution and acqui-
sition time, as discussed in the following sections.
VDD
The ADXL202/ADXL210 have two power supply (VDD) Pins:
13 and 14. These two pins should be connected directly together.
COM
The ADXL202/ADXL210 have two commons, Pins 4 and 7.
These two pins should be connected directly together and Pin 7
grounded.
VTP
This pin is to be left open; make no connections of any kind to
this pin.
Decoupling Capacitor CDC
A 0.1
µF capacitor is recommended from V
DD to COM for
power supply decoupling.
ST
The ST pin controls the self-test feature. When this pin is set to
VDD, an electrostatic force is exerted on the beam of the acceler-
ometer. The resulting movement of the beam allows the user to
test if the accelerometer is functional. The typical change in
output will be 10% at the duty cycle outputs (corresponding to
800 mg). This pin may be left open circuit or connected to
common in normal use.
Duty Cycle Decoding
The ADXL202/ADXL210’s digital output is a duty cycle modu-
lator. Acceleration is proportional to the ratio T1/T2. The
nominal output of the ADXL202 is:
0 g = 50% Duty Cycle
Scale factor is 12.5% Duty Cycle Change per g
The nominal output of the ADXL210 is:
0 g = 50% Duty Cycle
Scale factor is 4% Duty Cycle Change per g
These nominal values are affected by the initial tolerance of the
device including zero g offset error and sensitivity error.
T2 does not have to be measured for every measurement cycle.
It need only be updated to account for changes due to tempera-
ture, (a relatively slow process). Since the T2 time period is
shared by both X and Y channels, it is necessary only to mea-
sure it on one channel of the ADXL202/ADXL210. Decoding
algorithms for various microcontrollers have been developed.
Consult the appropriate Application Note.




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