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ADC14DS105 Arkusz danych(PDF) 5 Page - Texas Instruments |
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ADC14DS105 Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 14 page 4 SIGNAL PATH designer signal A and prevent recovery at baseband. Figure 3c shows the required bandpass filter. Often in an under-sampled system, the signal bandwidth of interest is over-sampled, such as a 100 MSPS sampling of a 5 MHz-bandwidth signal, and post-filtered digitally to improve the dynamic range of the system. Noise-processing gain is obtained by the fact that the ADC’s input referred noise is spread over the entire 1st Nyquist zone from zero to fS/2. By restricting the input bandwidth to less than fS/2, the noise at the input of the ADC is reduced, giving increased dynamic range and resolution. The added processing gain is given by the equation: Processing Gain = 10 log [(fs/2)/ BW] dB where BW is the post-filtered signal bandwidth. For fS = 100 MSPS and BW = 5 MHz, this equates to a 10 dB-processing gain. To maximize process- ing gain, over-sample the signal bandwidth at the highest-possible sample rate, and post-process the narrowest-possible signal bandwidth. Under-sampling is employed in many modern radio and RADAR systems where a single, analog-mixer stage down-converts an RF signal to an IF signal which, after bandpass filtering, is aliased to digital baseband where the final signal is extracted by further digital processing. This reduces the number of analog-mixer and filter stages. Under-sampling the input signal is equivalent to a baseband ADC plus IF down-conversion mixer. The downside of under-sampling is the higher-frequency perfor- mance required from the amplifier and ADC, more stringent jitter requirements on the ADC clock, and the requirements for DSP processing. Sampling Clock Considerations Clock jitter on the ADC clock is another key factor affecting the sampling system Signal-to-Noise Ratio (SNR). At high-input-signal frequencies, the SNR of the ADC departs from the familiar quantiza- tion-noise-limited level of 6.02n + 1.76 dB (where n = number of bits) to the jitter-noise-limited level of -20 x log(2π x fSIGNAL x tjrms). The variable fSIGNAL is the highest-input-signal- frequency component for conversion by the ADC. The variable tjrms is the total-rms clock jitter in seconds, given by the root-sum square of all the rms-timing jitter components from the different stages in the clock path including the clock source, clock buffer, and the internal-clock circuit within the ADC. For example, to obtain 74 dB-SNR performance at 300 MHz requires the total rms jitter in the clock path including the ADC to be less than 105 femto seconds (fs) rms. National’s newest high-sample- rate converters are specified with 2 VP-P differential clocks to minimize jitter and maximize SNR. It is important to drive these inputs with low-jitter clocks. For instance, a 70 fs, external-clock-path jitter com- bined with a 70 fs, internal-ADC-clock jitter delivers 100 fs total jitter (combined in rss fashion). National offers a family of low-jitter-clock components targeted at this application. ADC Input Stage When choosing an amplifier to drive a high-speed ADC, it is important to understand the load that the amplifier is required to drive. The internal front end of an unbuffered ADC typically consists of a sampling-input network controlled by a sample- and-hold clock signal which commands the input network to either sample the applied input signal or hold the input state for conversion (Figure 4). This input network presents a changing capacitive load to the driver stage as it transitions repeatedly between sample and hold, causing transient charg- ing spikes at the ADC input, which are made worse 1st Frequency Nyquist Zone Wanted Input Signal A 2nd Nyquist Zone 3rd Nyquist Zone 4th Nyquist Zone 5th Nyquist Zone 6th Nyquist Zone 7th Nyquist Zone 8th Nyquist Zone 9th Nyquist Zone 10th Nyquist Zone 11th Nyquist Zone 12th Nyquist Zone Unwanted Signal B Alias of A Bandpass Filter 2f s fs 3f s 4f s 5f s Figure 3c. Unwanted signal B prevented from aliasing B by bandpass filter around A Selecting Amplifiers, ADCs, and Clocks for High-Performance Signal Paths SignalPathDesigner.indd 4 SignalPathDesigner.indd 4 9/5/07 3:24:33 PM 9/5/07 3:24:33 PM |
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