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T8531A Arkusz danych(PDF) 11 Page - Agere Systems

Numer części T8531A
Szczegółowy opis  T8531A/8532 Multichannel Programmable Codec Chip Set
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Agere Systems Inc.
11
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Pin Information (continued)
Table 2. T8531A Pin Descriptions (continued)
* The DSP is not configured for boundary scan operation.
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates that a pull-
up device is included on this lead, Id indicates that a pull-down device is included on this lead.
Number
Name
Type
Name/Function
23
SDX
TO
Transmit PCM Output. This pin remains in the high-impedance state
except during the transmit time slots as defined in the TSA registers.
Data is shifted out on the rising edge of SCK.
21
SFS
TI
Frame Sync. Active-high pulse or square wave with an 8 kHz pulse
repetition rate. The rising edge defines the start of the transmit and
receive frames.
54
CDO
CO
T8532 Control Data Output. Control register information for the T8532
chips. Data is valid only when either CCS0 or CCS1 is low.
51
CDI
TIu
T8532 Control Data Input. Control register information from the T8532
chips. Data is valid only when either CCS0 or CCS1 is low. An internal
pull-up device is provided.
53, 52
CCS[1:0]
CO
Control Interface Chip Select (Active-Low). These active-low outputs
select one of the associated T8532 chips.
7TCK
TI
JTAG Test Port*-Common Test Clock. Rate
≤20 MHz.
4TDI
TIu
JTAG Test Port*-Serial Data Input. A pull-up device is provided.
5TDO
TO
JTAG Test Port*-Serial Data Output.
6TMS
TIu
JTAG Test Port*-Mode Select. A pull-up device is provided.
48
JTESTB
TIu
JTAG Test. Used for factory testing. Do not make any connection to this
pin. A pull-up device is provided.
59
HIGHZB
TIu
3-State Control Pin (Active-Low). When pulled low, the device output
pins go into a high-impedance state. A pull-up device is provided.
60
TEST
CIu
Test Mode Input (Active-Low). This input allows bypass of clock synthe-
sizer and uses TSTCLK to drive the chip. A pull-up device is provided.
61
CK16
CO
16 MHz Clock Output. 16.384 MHz clock output (50% duty cycle). This
clock is present at all times and can be used to drive a host processor.
8TSTCLK
CI
Test Clock.
1, 12, 14, 64
NC
No Connect. This pin may be used as a tie point.
55
T_SYNC
CIu
Test Sync (Active-Low). Used for factory testing. Do not make any con-
nection to this pin. A pull-up device is provided.
58
RSTB
TIu
Reset (Active-Low). A logic low initiates reset. A pull-up device is pro-
vided.
3, 10, 16, 19,
25, 31, 34, 46,
50, 56, 62
VDD
5 V Digital Power Supply. Power supply decoupling capacitors (0.1
µF)
should be connected from each VDD pin to ground. Capacitors should be
located as close as possible to the device pins.
2, 9, 15, 18, 26,
32, 33, 41, 47,
49, 57, 63
VSS
Digital Ground.


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