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T8531A Arkusz danych(PDF) 20 Page - Agere Systems

Numer części T8531A
Szczegółowy opis  T8531A/8532 Multichannel Programmable Codec Chip Set
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Agere Systems Inc.
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Chip Set Functional Description
(continued)
DSP Engine Timing (continued)
Changing DSP RAM Space of an Active Time Slot
The microprocessor is only allowed to change four
RAM locations for an active time slot:
s
Relative transmit gain
s
Relative receive gain
s
Address of receive ac routine
s
Address of transmit ac routine
Absolute gains and time-slot assignment can only be
altered when the time slot is inactive. Note that the
DSP engine does not check the TCW of active time
slots.
Following the initial powerup, the line card is likely to be
in service without being reset for as long as it continues
to operate trouble-free. Therefore, the microprocessor
has the option of continuously monitoring the variables
it has programmed by reading them back from the DSP
engine/microprocessor interface and rewriting them.
DSP Engine Memory Requirements
The size of the DSP engine internal dual-port RAM is
4K x 16-bit words per DSP engine. RAM storage is
used for user-programmable variables and for interme-
diate storage of the data being processed by the
device. The RAM memory map is given in Table 18.
The on-chip ROM is used for both program and data.
The DSP engine firmware is ROM based. The hard-
ware development system code is also ROM based.
The DSP engine ROM memory map is given in
Table 41.
T8531A Reset and Start-Up
The chips support both hardware and software reset.
Hardware Reset
The T8531A reset functions are handled by the reset
control block. Hardware reset occurs if the board is
powered up with RSTB low. Since RSTB has a Schmitt
trigger buffer with an internal pull-up, a capacitor
attached external to the RSTB pin causes the pin to
pull high after a specified period of time. For power-on
reset, the T8531A requires that this period of time be
>1 ms to give the on-chip clock synthesizer block time
to start producing clock edges for the T8531A and
T8532 chips (although it may not have reached its final
accuracy yet). Successful hardware reset of the device
requires that:
1. The PCM bus signals SCK and SFS should be valid
at the start of the 1 ms power-on reset period.
2. VDD (and therefore RSTB) should have been low for
at least 200 ms prior to commencing power-on reset
to ensure that the JTAG controller powerup reset cir-
cuit has had time to clear the JTAG controller.
If, during normal operation, VDD falls below the defined
minimum value, VDD min, the power-on reset procedure
described above must be repeated.
Hardware reset occurs if RSTB is pulsed high-low-high
for 1 ms during normal operation (i.e., no loss of
power).
Table 7. Summary of Microprocessor Commands for Control of T8531A Data Processing
Function Required
Number of Commands
When Issued
Bulk TSA register download & BCW2
17
Start-up
Individual TSA register download
1
Prior to activating a time slot via the TCW
Coefficient download
16 per channel
Start-up or when time slot is inactive
Set TCW to use/share coefficients
already downloaded to default tables
1
Start-up or when time slot is inactive
Enable time slot via TCW (fixed TSA)
1
When time slot is inactive
Enable time slot via TCW (dynamic TSA)
2
When time slot is inactive
Disable time slot
1
When time slot is active
Change gain value
1 per gain
Any time


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