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T8531A Arkusz danych(PDF) 3 Page - Agere Systems

Numer części T8531A
Szczegółowy opis  T8531A/8532 Multichannel Programmable Codec Chip Set
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Producent  AGERE [Agere Systems]
Strona internetowa  http://www.agere.com
Logo AGERE - Agere Systems

T8531A Arkusz danych(HTML) 3 Page - Agere Systems

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Preliminary Data Sheet
September 2001
Agere Systems Inc.
3
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Table of Contents (continued)
Figures
Page
Figure 1. System Block Diagram .................................1
Figure 2. Block Diagram of T8532 Octal Converter.....4
Figure 3. Block Diagram of One T8532 Analog
Channel........................................................4
Figure 4. T8531A Block Diagram ................................5
Figure 5. T8531A Digital ac Path.................................6
Figure 6. Control, PCM, and Octal Interfaces..............6
Figure 7. T8532 64-Pin MQFP ....................................7
Figure 8. T8531A 64-Pin TQFP...................................9
Figure 9. Timing Characteristics of PCM Interface
Assuming 2.048 MHz SCK Rate ................31
Figure 10. Timing Diagram for Microprocessor
Write/Read to/from the DSP on the
Control Interface.......................................32
Figure 11. Line Card Solution Using the L7585
SLIC .........................................................44
Figure 12. Line Card Solution Using the L9215G
SLIC .........................................................45
Figure 13. Line Card Solution Using the L9310G
SLIC .........................................................46
Figure 14. Common 2.4 V Voltage Reference...........47
Tables
Page
Table 1. T8532 Pin Descriptions ................................. 8
Table 2. T8531A Pin Descriptions ............................. 10
Table 3. Active Time-Slot Spacing in a PCM
Bus Frame ................................................... 15
Table 4. DSP Engine RAM Map for Channel_0 ac
Path Coefficients ......................................... 17
Table 5A. Bit Map for DSP Engine Time-Slot
Control Word............................................. 18
Table 5B. Bit Map for Default Per-Board
Coefficient Tables...................................... 18
Table 6. DSP Engine RAM Map for Time-Slot
Information Table 0...................................... 18
Table 7. Summary of Microprocessor Commands
for Control of T8531A Data Processing ....... 20
Table 8. Digital Interface............................................ 25
Table 9. Analog Interface .......................................... 25
Table 10. T8532 Power Dissipation........................... 26
Table 11. T8531A Power Dissipation ........................ 26
Table 12. Gain and Dynamic Range ......................... 26
Table 13. Noise (per Channel) .................................. 28
Table 14. Distortion and Group Delay ....................... 29
Table 15. Crosstalk.................................................... 29
Table 16. PCM Interface Timing ............................... 30
Table 17. Serial Control Port Timing ........................ 32
Table 18. DSP Engine RAM Memory Map ................33
Table 19. T8531A Time-Slot Assignment Memory
Map ...........................................................35
Table 20A. Bit Map for T8531A Time-Slot Assignment
Registers at 0x1400—0x140F.................35
Table 20B. Bit Map for CTZ Disable and Null
Channel...................................................35
Table 21. T8531A Channel Register Memory Map
for T8532 Device 0 ...................................36
Table 22. T8531A Channel Register Memory Map
for T8532 Device 1 ...................................36
Table 23. Bit Map for T8532 Powerup/Powerdown
Registers at 0x1500—0x1507 and
0x1540—0x1547 .......................................37
Table 24. Bit Map for T8532 Channel Control
Register 1 at 0x1508—0x150F and
0x1548—0x154F .......................................37
Table 25. T8532 Control Register 1: Transmit
Gain ...........................................................37
Table 26. T8532 Control Register 1: Analog
Termination Impedance .............................37
Table 27. T8532 Control Register 1: Digital
Loopback ...................................................38
Table 28. Bit Map for T8532 All Channel Test
Register at 0x1510 and 0x1550.................38
Table 29. Bits 3:0 of T8532 All Channel Test
Register at 0x1510 and 0x1550.................38
Table 30. Bit Map for T8532 Channel Control
Register 2 at 0x1518—0x151F and
0x1558—0x155F .......................................39
Table 31. T8532 Control Register 2: Receive Gain ...39
Table 32. T8531A Control Register Map ...................39
Table 33. Bits 15:8 of T8531A Board Control Word 1
at 0x1FFE ..................................................40
Table 34. Bits 7:0 of T8531A Board Control Word 1
at 0x1FFE ..................................................40
Table 35. Bits 15:9 of T8531A Board Control Word 2
at 0x1FFC..................................................41
Table 36. Bits 8:0 of T8531A Board Control Word 2
at 0x1FFC..................................................41
Table 37. Bits 15:0 of T8531A Board Control Word 3
at 0x1FFA ..................................................41
Table 38. Bits 15:0 of T8531A Board Control Word 4
at 0x1FF8 ..................................................41
Table 39. Bits 15:0 of T8531A Board Control Word 5
at 0x1FF6 ..................................................41
Table 40. Bits 15:0 of T8531A Reset of
Microprocessor Commands at 0x7FFF .....41
Table 41. DSP Engine ROM Memory Map................42
Table 42. Transmit Path Group Delay vs. Bit Offset ..50


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