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T8531A Arkusz danych(PDF) 5 Page - Agere Systems

Numer części T8531A
Szczegółowy opis  T8531A/8532 Multichannel Programmable Codec Chip Set
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Producent  AGERE [Agere Systems]
Strona internetowa  http://www.agere.com
Logo AGERE - Agere Systems

T8531A Arkusz danych(HTML) 5 Page - Agere Systems

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Agere Systems Inc.
5
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
General Description (continued)
T8531A Description
As shown in Figure 4, the T8531A contains a digital signal processor (DSP) engine surrounded by a customized
input/output (I/O) frame. The I/O frame performs the
µ-law or A-law conversion as well as the decimation and inter-
polation functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The
sigma-delta converters operate at a 1.024 MHz sample rate, while the signal processor operates at 16 ksamples/s.
A key function of the I/O frame is to control the timing of the digital data going to the signal processor so that group
delay is minimized.
The I/O frame also contains an integrated phase-locked loop which synthesizes all the required internal clocks for
the chip set.
The microcontroller interface is used to run the ROM routines and to download the gain, filter, and balance network
settings, powerup/powerdown commands, time-slot assignments, digital loopback settings, and commands for the
T8532 octal chips.
0505(F)
Figure 4. T8531A Block Diagram
PLL
CLOCK
SYNTHESIZER
JTAG
SYSTEM PCM INTERFACE
DATA TRANSFER
µ/A-LAW CONVERTER
MICRO-
PROCESSOR
CONTROL
INTERFACE
DSP
ROM
DSP
RAM
DIGITAL
SIGNAL
PROCESSING
ENGINE
DECIMATOR
INTERPOLATOR
TSA
T8532 CONTROL INTERFACE
T8532 OVERSAMPLED INTERFACE
UPCK
UPDI
UPDO
TSTCLK
VDD
VSS
HDS
UPCS
HIGHZB
RSTB
T_SYNC
TEST
OSDX/R[3:0]


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