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AD5697R Arkusz danych(PDF) 6 Page - Analog Devices |
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AD5697R Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 28 page AD5697R Data Sheet Rev. 0 | Page 6 of 28 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2. Table 4. Parameter1 Min Max Unit Test Conditions/Comments t1 2.5 µs SCL cycle time t2 0.6 µs SCL high time, tHIGH t3 1.3 µs SCL low time, tLOW t4 0.6 µs Start/repeated start condition hold time, tHD,STA t5 100 ns Data setup time, tSU,DAT t62 0 0.9 µs Data hold time, tHD,DAT t7 0.6 µs Setup time for repeated start, tSU,STA t8 0.6 µs Stop condition setup time, tSU,STO t9 1.3 µs Bus free time between a stop and a start condition, tBUF t10 0 300 ns Rise time of SCL and SDA when receiving, tR t11 20 + 0.1CB3 300 ns Fall time of SDA and SCL when transmitting/receiving, tF t12 20 ns LDAC pulse width t13 400 ns SCL rising edge to LDAC rising edge CB3 400 pF Capacitive load for each bus line 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the falling edge of the SCL. 3 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. Figure 2. 2-Wire Serial Interface Timing Diagram SCL SDA t1 t3 LDAC1 LDAC2 START CONDITION REPEATED START CONDITION STOP CONDITION NOTES 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. t4 t6 t5 t7 t8 t2 t13 t4 t11 t10 t12 t12 t9 |
Podobny numer części - AD5697R |
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Podobny opis - AD5697R |
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