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74AC175, 74ACT175 Rev. 1.4

2

Logic Symbol

IEEE/IEC

Functional Description

The AC/ACT175 consists of four edge-triggered D-type

flip-flops with individual D inputs and Q and Q outputs.

The Clock and Master Reset are common. The four flip-

flops will store the state of their individual D inputs on the

LOW-to-HIGH clock (CP) transition, causing individual Q

and Q outputs to follow. A LOW input on the Master

Reset (MR) will force all Q outputs LOW and Q outputs

HIGH independent of Clock or Data inputs. The AC/

ACT175 is useful for general logic applications where a

common Master Reset and Clock are acceptable.

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Figure 1.

LL

H

HH

L