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74ACT715-RPC Arkusz danych(PDF) 4 Page - Fairchild Semiconductor |
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74ACT715-RPC Arkusz danych(HTML) 4 Page - Fairchild Semiconductor |
4 / 14 page www.fairchildsemi.com 4 Signal Specification HORIZONTAL SYNC AND BLANK SPECIFICATIONS All horizontal signals are defined by a start and end time. The start and end times are specified in number of clock cycles per line. The start of the horizontal line is considered pulse 1 not 0. All values of the horizontal timing registers are referenced to the falling edge of the Horizontal Blank signal (see Figure 1). Since the first CLOCK edge, CLOCK #1, causes the first falling edge of the Horizontal Blank ref- erence pulse, edges referenced to this first Horizontal edge are n + 1 CLOCKs away, where “n” is the width of the tim- ing in question. Registers 1, 2, and 3 are programmed in this manner. The horizontal counters start at 1 and count until HMAX. The value of HMAX must be divisible by 2. This limitation is imposed because during interlace opera- tion this value is internally divided by 2 in order to generate serration and equalization pulses at 2 × the horizontal fre- quency. Horizontal signals will change on the falling edge of the CLOCK signal. Signal specifications are shown below. FIGURE 1. Horizontal Waveform Specification Horizontal Period (HPER) = REG(4) × ckper Horizontal Blanking Width: = [REG(3) − 1] × ckper Horizontal Sync Width: = [REG(2) − REG(1)] × ckper Horizontal Front Porch: = [REG(1) − 1] × ckper VERTICAL SYNC AND BLANK SPECIFICATION All vertical signals are defined in terms of number of lines per frame. This is true in both interlaced and noninterlaced modes of operation. Care must be taken to not specify the Vertical Registers in terms of lines per field. Since the first CLOCK edge, CLOCK #1, causes the first falling edge of the Vertical Blank (first Horizontal Blank) reference pulse, edges referenced to this first edge are n + 1 lines away, where “n” is the width of the timing in question. Registers 5, 6, and 7 are programmed in this manner. Also, in the inter- laced mode, vertical timing is based on half-lines. There- fore registers 5, 6, and 7 must contain a value twice the total horizontal (odd and even) plus 1 (as described above). In non-interlaced mode, all vertical timing is based on whole-lines. Register 8 is always based on whole-lines and does not add 1 for the first clock. The vertical counter starts at the value of 1 and counts until the value of VMAX. No restrictions exist on the values placed in the vertical registers. Vertical Blank will change on the leading edge of HBLANK. Vertical Sync will change on the leading edge of HSYNC. (See Figure 2.) Vertical Frame Period (VPER) = REG(8) × hper Vertical Field Period (VPER/n) = REG(8) × hper/n Vertical Blanking Width = [REG(7) − 1] × hper/n Vertical Syncing Width = [REG(6) − REG(5)] × hper/n Vertical Front Porch = [REG(5) − 1] × hper/n where n = 1 for noninterlaced n = 2 for interlaced COMPOSITE SYNC AND BLANK SPECIFICATION Composite Sync and Blank signals are created by logically ANDing (ORing) the active LOW (HIGH) signals of the cor- responding vertical and horizontal components of these signals. The Composite Sync signal may also include ser- ration and/or equalization pulses. The Serration pulse inter- val occurs in place of the Vertical Sync interval. Equalization pulses occur preceding and/or following the Serration pulses. The width and location of these pulses can be programmed through the registers shown below. (See Figure 3.) Horizontal Equalization PW = [REG(9) − REG(1)] × ckper REG 9 = (HFP) + (HEQP) + 1 Horizontal Serration PW: = [REG(4)/n + REG(1) − REG(10)] × ckper REG 10 = (HFP) + (HPER/2) − (HSERR) + 1 Where n = 1 for noninterlaced single serration/equal- ization n = 2 for noninterlaced double serration/equal- ization n = 2 for interlaced operation |
Podobny numer części - 74ACT715-RPC |
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Podobny opis - 74ACT715-RPC |
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