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74LVTH652 Arkusz danych(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH652 Arkusz danych(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Pin Descriptions Connection Diagram Truth Table (Note 1) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW to HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description A0–A7 Data Register A Inputs/ 3-STATE Outputs B0–B7 Data Register B Inputs/ 3-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs Inputs Inputs/Outputs Operating Mode OEAB OEBA CPAB CPBA SAB SBA A0 thru A7 B0 thru B7 L H H or L H or L X X Input Input Isolation LH X X Store A and B Data XH H or L X X Input Not Specified Store A, Hold B HH X X Input Output Store A in Both Registers LX H or L X X Not Specified Input Hold A, Store B LL X X Output Input Store B in Both Registers L L X X X L Output Input Real-Time B Data to A Bus L L X H or L X H Store B Data to A Bus H H X X L X Input Output Real-Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus |
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