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74VHC157SJ Arkusz danych(PDF) 1 Page - Fairchild Semiconductor |
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74VHC157SJ Arkusz danych(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page November 1992 Revised April 1999 © 1999 Fairchild Semiconductor Corporation DS011536.prf www.fairchildsemi.com 74VHC157 Quad 2-Input Multiplexer General Description The VHC157 is an advanced high speed CMOS Quad 2- Channel Multiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It consists of four 2-input digital multiplexers with common select and enable inputs. When the ENABLE input is held “H” level, selection of data is inhibited and all the outputs become “L” level. The SELECT decoding determines whether the I0x or I1x inputs get routed to their correspond- ing outputs. An Input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and on two supply systems such as battery back up. This circuit prevents device destruction due to mismatched sup- ply and input voltages. Features s High Speed: tPD = 4.1 ns (typ) at VCC = 5V s Low power dissipation: ICC = 4 µA (max.) at TA = 25°C s High noise immunity: VNIH = VNIL = 28% VCC (min.) s Power down protection is provided on all inputs s Low noise: VOLP = 0.8V (max.) s Pin and function compatible with 74HC157 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Number Package Description 74VHC157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC157N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Pin Names Description I0a–I0d Source 0 Data Inputs I1a–I1d Source 1 Data Inputs E Enable Input S Select Input Za–Zd Outputs |
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