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CD4724BC Arkusz danych(PDF) 4 Page - Fairchild Semiconductor |
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CD4724BC Arkusz danych(HTML) 4 Page - Fairchild Semiconductor |
4 / 7 page www.fairchildsemi.com 4 AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + CL) VCC 2f + P Q; where CL = load capacitance; f = frequency of operation; for further details, see Application Note AN-90, “Family Characteristics”. Symbol Parameter Conditions Min Typ Max Units tPHL, tPLH Propagation Delay VDD = 5V 200 400 ns Data to Output VDD = 10V 75 150 ns VDD = 15V 50 100 ns tPLH, tPHL Propagation Delay VDD = 5V 200 400 ns Enable to Output VDD = 10V 80 160 ns VDD = 15V 60 120 ns tPHL Propagation Delay VDD = 5V 175 350 ns Clear to Output VDD = 10V 80 160 ns VDD = 15V 65 130 ns tPLH, tPHL Propagation Delay VDD = 5V 225 450 ns Address to Output VDD = 10V 100 200 ns VDD = 15V 75 150 ns tTHL, tTLH Transition Time VDD = 5V 100 200 ns (Any Output) VDD = 10V 50 100 ns VDD = 15V 40 80 ns TWH, TWL Minimum Data VDD = 5V 100 200 ns Pulse Width VDD = 10V 50 100 ns VDD = 15V 40 80 ns tWH, tWL Minimum Address VDD = 5V 200 400 ns Pulse Width VDD = 10V 100 200 ns VDD = 15V 65 125 ns tWH Minimum Clear VDD = 5V 75 150 ns Pulse Width VDD = 10V 40 75 ns VDD = 15V 25 50 ns tSU Minimum Setup Time VDD = 5V 40 80 ns Data to E VDD = 10V 20 40 ns VDD = 15V 15 30 ns tH Minimum Hold Time VDD = 5V 60 120 ns Data to E VDD = 10V 30 60 ns VDD = 15V 25 50 ns tSU Minimum Setup Time VDD = 5V −15 50 ns Address to E VDD = 10V 0 30 ns VDD = 15V 0 20 ns tH Minimum Hold Time VDD = 5V −50 15 ns Address to E VDD = 10V −20 10 ns VDD = 15V −15 5 ns CPD Power Dissipation Per Package 100 pF Capacitance (Note 5) CIN Input Capacitance Any Input 5.0 7.5 pF |
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