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CD4724BC Arkusz danych(PDF) 1 Page - Fairchild Semiconductor |
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CD4724BC Arkusz danych(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page October 1987 Revised January 1999 © 1999 Fairchild Semiconductor Corporation DS006003.prf www.fairchildsemi.com CD4724BC 8-Bit Addressable Latch General Description The CD4724BC is an 8-bit addressable latch with three address inputs (A0–A2), an active low enable input (E), active high clear input (CL), a data input (D) and eight out- puts (Q0–Q7). Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VDD (typ.) s Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS s Serial to parallel capability s Storage register capability s Random (addressable) data entry s Active high demultiplexing capability s Common active high clear Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View Truth Table Order Number Package Number Package Description CD4724BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4724BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Mode Selection E CL Addressed Unaddressed Mode Latch Latch L L Follows Data Holds Previous Data Addressable Latch H L Hold Previous Data Holds Previous Data Memory L H Follows Data Reset to “0” Demultiplexer H H Reset to “0” Reset to “0” Clear |
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