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AD8195ACPZ Arkusz danych(PDF) 1 Page - Analog Devices |
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AD8195ACPZ Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 20 page HDMI/DVI Buffer with Equalization Data Sheet AD8195 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved. FEATURES 1 input, 1 output HDMI/DVI link Enables HDMI 1.3a-compliant front panel input 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs for operation with long HDMI cables (20 m at 2.25 Gbps) Preemphasized outputs Fully buffered unidirectional inputs/outputs 50 Ω on-chip terminations Low added jitter Transmitter disable feature Reduces power dissipation Disables input termination 3 auxiliary buffered channels per link Bidirectional buffered DDC lines (SDA and SCL) Bidirectional buffered CEC line with integrated pull-up resistors (27 kΩ) Independently powered from 5 V of HDMI input connector Logic level translation (3.3 V, 5 V) Input/output capacitance isolation Standards compatible: HDMI, DVI, HDCP, DDC, CEC 40-lead LFCSP_VQ package (6 mm × 6 mm) APPLICATIONS Front panel buffer for advanced television (HDTV) sets GENERAL DESCRIPTION The AD8195 is an HDMI/DVI buffer featuring equalized TMDS inputs and preemphasized TMDS outputs, ideal for systems with long cable runs. The AD8195 includes bidirectional buffering for the DDC bus and bidirectional buffering with integrated pull-up resistors for the CEC bus. The DDC and CEC buffers are powered independently of the TMDS buffers so that DDC/ CEC functionality can be maintained when the system is powered off. The AD8195 meets all the requirements for sink tests as defined in Section 8 of the HDMI Compliance Test 1.3c. The AD8195 is specified to operate over the −40°C to +85°C temperature range. FUNCTIONAL BLOCK DIAGRAM IP[3:0] IN[3:0] VTTI OP[3:0] AMUXVCC AVEE VTTO AVCC ON[3:0] VREF_IN VREF_OUT + – + – EQ BUFFER PE CONTROL LOGIC 4 4 4 2 2 4 HIGH SPEED BUFFERED LOW SPEED BUFFERED PARALLEL BIDIRECTIONAL AD8195 SCL_IN SDA_IN SCL_OUT SDA_OUT CEC_IN CEC_OUT Figure 1. TYPICAL APPLICATION MEDIA CENTER SET-TOP BOX DVD PLAYER HDTV SET 4:1 HDMI SWITCH AD8195 HDMI RECEIVER FRONT PANEL CONNECTOR BACK PANEL CONNECTORS GAME CONSOLE Figure 2. Typical AD8195 Application for HDTV Sets PRODUCT HIGHLIGHTS 1. Enables a fully HDMI 1.3a-compliant front panel input. 2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep color (12-bit color) HDMI formats and greater than UXGA (1600 × 1200) DVI resolutions. 3. Input cable equalizer enables use of long cables; more than 20 meters (24 AWG) at data rates of up to 2.25 Gbps. 4. Auxiliary buffer isolates and buffers the DDC bus and CEC line for a single chip, fully HDMI 1.3a-compliant solution. 5. Auxiliary buffer is powered independently from the TMDS link so that DDC/CEC functionality can be maintained when the system is powered off. |
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