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DM74S299 Arkusz danych(PDF) 4 Page - Fairchild Semiconductor |
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DM74S299 Arkusz danych(HTML) 4 Page - Fairchild Semiconductor |
4 / 5 page www.fairchildsemi.com 4 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Note 8: TA = 25°C and VCC = 5V. Note 9: All typicals are at VCC = 5V, TA = 25°C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics at VCC = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load) Note 11: CL = 5 pF. Note 12: RL = 1KΩ for delays measured to QA′ and QH′. Note 13: For testing fMAX all outputs are loaded simultaneously. Symbol Parameter Conditions Min Typ Max Units (Note 8) VI Input Clamp Voltage VCC = Min, II = −18 mA −1.2 V VOH HIGH Level VCC = Min, IOH = Max QA thru QH 2.4 3.2 V Output Voltage VIL = Max, VIH = Min QA′, QH′ 2.7 3.4 VOL LOW Level VCC = Min, IOL = Max 0.5 V Output Voltage VIH = Min, VIL = Max II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA IIH HIGH Level VCC = Max A thru H, 100 Input Current VI = 2.7V S0, S1 µA Any Other 50 IIL LOW Level VCC = Max Clock, Clear −2 Input Current VI = 0.5V S0, S1 −0.5 mA Other −0.25 IOZH Off-State Output Current with VCC = Max, VO = 2.4V HIGH Level Output Voltage VIH = Min, VIL = Max 100 µA Applied (QA thru QH) IOZL Off-State Output Current with VCC = Max, VO = 0.5V LOW Level Output Voltage VIH = Min, VIL = Max −250 µA Applied (QA thru QH) IOS Short Circuit Output VCC = Max −40 −100 mA Current (QA thru QH) (Note 10) Short Circuit Output VCC = Max −20 −100 Current (QA′, QH′) (Note 10) ICC Supply Current VCC = Max 140 225 mA RL = 280Ω (Note 12) Symbol Parameter From (Input) CL = 15 pF CL = 50 pF Units To (Output) Min Max Min Max fMAX Maximum Clock Frequency (Note 13) 50 40 MHz tPLH Propagation Delay Time Clock to QA′ or QH′ 20 22 ns LOW-to-HIGH Level Output (Note 12) tPHL Propagation Delay Time Clock to QA′ or QH′ 20 23 ns HIGH-to-LOW Level Output (Note 12) tPLH Propagation Delay Time Clock to QA thru QH 21 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock to QA thru QH 21 ns HIGH-to-LOW Level Output tPHL Propagation Delay Time Clear to QA′ or QH′ 21 24 ns HIGH-to-LOW Level Output (Note 12) tPHL Propagation Delay Time Clear to QA thru QH 24 ns HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output G1, G2 to QA thru QH 18 ns tPZL Output Enable Time to LOW Level Output G1, G2 to QA thru QH 18 ns tPHZ Output Disable Time to HIGH Level Output (Note 11) G1, G2 to QA thru QH 12 ns tPLZ Output Disable Time to LOW Level Output (Note 11) G1, G2 to QA thru QH 12 ns |
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